公开(公告)号：US20070172690A1

公开(公告)日：2007-07-26

申请号：US11399499

申请日：2006-04-07

Applicant: Si-suk Kim ,  Kwang-su Yu ,  Dong-chun Lee ,  Jae-hoon Choi

Inventor： Si-suk Kim ,  Kwang-su Yu ,  Dong-chun Lee ,  Jae-hoon Choi

IPC: B32B15/01

CPC classification number: H05K3/3436 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/262 ,  B23K2101/40 ,  B32B15/01 ,  B32B15/018 ,  C22C13/00 ,  C22C13/02 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16225 ,  H05K3/3463 ,  H05K3/3473 ,  H05K3/3484 ,  H05K2201/10992 ,  Y02P70/613 ,  Y10T428/12708 ,  H01L2924/00014

Abstract: A joining method, a method of mounting a semiconductor package (PKG) using the same, and a substrate-joining structure prepared thereby are provided. The joining method may comprise placing a first junction composition including tin and silver, and a second junction composition, including tin and bismuth to contact each other and forming a junction by performing a thermal treatment on the junction compositions at a temperature of at least 170° C. or higher.

Abstract translation: 提供了一种接合方法，一种安装使用其的半导体封装（PKG）的方法以及由此制备的基片接合结构。 接合方法可以包括将包含锡和银的第一接合组合物和包含锡和铋的第二接合组合物彼此接触并通过在接合组合物上在至少170°的温度下进行热处理形成接合部 C.或更高。

公开(公告)号：US20070170592A1

公开(公告)日：2007-07-26

申请号：US11717902

申请日：2007-03-13

Applicant: Chung Key ,  Mustapha Faizul ,  Tan Sang

Inventor： Chung Key ,  Mustapha Faizul ,  Tan Sang

IPC: H01L23/48

CPC classification number: H05K3/3436 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/136 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H05K3/3463 ,  H05K2201/10992 ,  Y02P70/613 ,  Y10T428/12486 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An apparatus that includes a first component defining an interior of the apparatus; a first solder composition exterior to the first component; a second solder composition exterior to the first solder composition and the first component; and a second component exterior to the second solder composition, the first solder composition, and the first component.

Abstract translation: 一种装置，包括限定所述装置内部的第一部件; 第一组分外部的第一焊料组合物; 在第一焊料组合物外面的第二焊料组合物和第一组分; 以及第二焊料组合物外部的第二组分，第一焊料组合物和第一组分。

公开(公告)号：US20070096282A1

公开(公告)日：2007-05-03

申请号：US11163771

申请日：2005-10-29

Applicant: IL Kwon Shim ,  Tsz Yin Ho ,  Dario S. Filoteo ,  Seng Guan Chow

Inventor： IL Kwon Shim ,  Tsz Yin Ho ,  Dario S. Filoteo ,  Seng Guan Chow

IPC: H01L23/02

CPC classification number: H01L24/83 ,  H01L23/49811 ,  H01L23/64 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/16 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/19107 ,  H05K1/141 ,  H05K3/321 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/10515 ,  H05K2201/10992 ,  H05K2203/0278 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An integrated circuit package system including a high-density small footprint system-in-package with a substrate is provided. Passive components are mounted on the substrate. Solder separators are provided on the substrate, the solder separators having flattened tops at a predetermined height above the substrate. A die is supported on the solder separators above the substrate.

Abstract translation: 提供了一种集成电路封装系统，其包括具有基板的高密度小尺寸封装体系。 无源元件安装在基板上。 焊料分离器设置在基板上，焊料分离器在基板上方的预定高度处具有平坦的顶部。 在基板上方的焊料分离器上支撑管芯。

公开(公告)号：US07042088B2

公开(公告)日：2006-05-09

申请号：US10796253

申请日：2004-03-10

Applicant: Tony H. Ho

Inventor： Tony H. Ho

IPC: H01L23/52

CPC classification number: H05K3/3436 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06505 ,  H01L2224/131 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16 ,  H01L2224/17051 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3463 ,  H05K2201/0379 ,  H05K2201/094 ,  H05K2201/10992 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The present invention includes a semiconductor package that forms the solder array joints on the die surface and corresponding BGA substrate and PCB respectively. The life times of array solder joints are increased through the use of two sets of array joints. The top array comprises a plurality of high melting solder joints and a plurality of low melting solder joints, while the bottom array comprises a plurality of high melting solder joints only. The reflow temperature of SMT assembly is between the aforementioned high melting point and low melting point of solder joints. In addition, each solder joint comprises a flat surface at its front edge.

Abstract translation: 本发明包括分别在模具表面上形成焊料阵列接头和相应的BGA基板和PCB的半导体封装。 阵列焊点的寿命通过使用两组阵列接头而增加。 顶部阵列包括多个高熔点焊接点和多个低熔点焊接点，而底部阵列仅包括多个高熔点焊接点。 SMT组装的回流温度在上述高熔点和低熔点焊点之间。 此外，每个焊接接头在其前边缘处包括平坦表面。

公开(公告)号：US20060091525A1

公开(公告)日：2006-05-04

申请号：US11265952

申请日：2005-11-03

Applicant: Saiki Hajime ,  Iba Masahiro

Inventor： Saiki Hajime ,  Iba Masahiro

IPC: H01L23/053

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L2224/81191 ,  H01L2924/01322 ,  H05K3/3452 ,  H05K3/3463 ,  H05K2201/09427 ,  H05K2201/099 ,  H05K2201/10992 ,  H05K2203/0465 ,  H05K2203/0594 ,  Y02P70/613 ,  H01L2924/00

Abstract: An electronic device comprised of a wiring board with a semiconductor component. The device is unlikely to have any defects, such as cracks to a solder joint portion during a reflow process of a flip-chip connection. The semiconductor component is flip-chip bonded at a pad array at a component side thereof to a pad array at a board side by way of an individual solder joint portion. In a solder resist layer at a semiconductor component side and a solder resist layer at a board side, D/D0 is prepared to be in a range of 0.70 to 0.99, where D is a bottom inner diameter of an opening at the board side and D0 is a bottom inner diameter of an opening at the component side.

Abstract translation: 一种由具有半导体部件的布线板构成的电子装置。 在倒装芯片连接的回流工艺期间，器件不太可能具有任何缺陷，例如焊接部分的裂纹。 半导体部件在其一侧的焊盘阵列处通过单独的焊接部分在基板侧被倒装成焊盘阵列。 在半导体部件侧的阻焊层和基板侧的阻焊层中，D / D 0为0.70〜0.99的范围，其中D为板侧开口的底部内径 D 0是部件侧的开口的底部内径。

公开(公告)号：US20060033214A1

公开(公告)日：2006-02-16

申请号：US10986385

申请日：2004-11-12

Applicant: Akira Tomono

Inventor： Akira Tomono

IPC: H01L23/48

CPC classification number: H01L24/16 ,  H01L21/563 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/75743 ,  H01L2224/83192 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/30105 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10977 ,  H05K2201/10992 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/3512 ,  H01L2924/0665

Abstract: A semiconductor device comprises a semiconductor element which is flip-chip bonded to a circuit substrate. The semiconductor element and the circuit substrate are flip-chip bonded using a sealing resin having flux function. The semiconductor element includes a solder bump formed on a first electrode pad through a first low melting point solder layer. The circuit substrate includes a second electrode pad corresponding to the first electrode pad, and a second low melting point solder layer is formed on the second electrode pad. The solder bump is bonded to the first and second electrode pads through the first and second low melting point solder layers.

Abstract translation: 半导体器件包括倒装芯片接合到电路基板的半导体元件。 使用具有助熔功能的密封树脂将半导体元件和电路基板倒装芯片接合。 半导体元件包括通过第一低熔点焊料层形成在第一电极焊盘上的焊料凸块。 电路基板包括对应于第一电极焊盘的第二电极焊盘，在第二电极焊盘上形成第二低熔点焊料层。 焊料凸点通过第一和第二低熔点焊料层结合到第一和第二电极焊盘。

公开(公告)号：US06828512B2

公开(公告)日：2004-12-07

申请号：US10267158

申请日：2002-10-08

Applicant: C. Key Chung ,  Sook Chien Chan ,  Kum Foo Leong

Inventor： C. Key Chung ,  Sook Chien Chan ,  Kum Foo Leong

IPC: H05K116

CPC classification number: H05K3/3436 ,  H05K1/113 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/09572 ,  H05K2201/10992 ,  H05K2203/043 ,  H05K2203/0455 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A substrate has at least one via-in-pad that includes a bond pad and a bore. In addition, the substrate has a plug coupled to the at least one via-in-pad, the plug has a first conductive material and adapted to couple with a solder ball having a second conductive material, the first conductive material having a higher reflow temperature than the second conductive material.

Abstract translation: 衬底具有至少一个包括焊盘和孔的通孔内焊盘。 另外，衬底具有耦合到至少一个通孔焊盘中的插塞，该插头具有第一导电材料并且适于与具有第二导电材料的焊料球耦合，第一导电材料具有较高的回流温度 比第二导电材料。

公开(公告)号：US06818090B2

公开(公告)日：2004-11-16

申请号：US09761594

申请日：2001-01-16

Applicant: Hans-Jürgen Hacke ,  Klaus-Peter Galuschki

Inventor： Hans-Jürgen Hacke ,  Klaus-Peter Galuschki

IPC: H01L23538

CPC classification number: H01L24/10 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/351 ,  H05K3/321 ,  H05K3/3436 ,  H05K2201/0212 ,  H05K2201/10234 ,  H05K2201/10992 ,  Y02P70/613 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49137 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49798 ,  Y10T156/1089 ,  H01L2924/00

Abstract: A semiconductor device in chip format having a chip which has at least one first insulating layer and electrical connection pads free of the insulating layer is described. On the first insulating layer, interconnects run from the electrical connection pads to base regions of external connection elements. A further applied insulating layer is provided with openings leading from the outside to the base regions of the external connection elements. In the openings there is a conductive adhesive, onto which small balls which are metallic at least on the outside are placed. The semiconductor element can also contain a solder paste instead of a conductive adhesive in the openings, and metallized small plastic balls are placed onto the solder paste. The invention furthermore relates to methods for producing the semiconductor device described.

Abstract translation: 描述了具有芯片的半导体器件，其芯片具有至少一个第一绝缘层和不含绝缘层的电连接焊盘。 在第一绝缘层上，互连从电连接焊盘延伸到外部连接元件的基极区域。 进一步施加的绝缘层设置有从外部连接到外部连接元件的基部区域的开口。 在开口中有导电粘合剂，至少在外部放置金属的小球。 半导体元件还可以在开口中包含焊膏代替导电粘合剂，并且将金属化的小塑料球放置在焊膏上。 本发明还涉及所述半导体器件的制造方法。

公开(公告)号：US20040212972A1

公开(公告)日：2004-10-28

申请号：US10422515

申请日：2003-04-24

Inventor： Leon M. Khilchenko ,  Mark W. Gailus

IPC: H05K001/11 ,  H01R012/04 ,  H01R012/16

CPC classification number: H05K3/4038 ,  H05K1/0298 ,  H05K3/321 ,  H05K3/3447 ,  H05K3/4046 ,  H05K3/4069 ,  H05K2201/0305 ,  H05K2201/0919 ,  H05K2201/10234 ,  H05K2201/1059 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/1446 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49165

Abstract: What is provided is a multi-layer PCB having a plurality of stacked dielectric layers, a conductor disposed on at least one of the plurality of dielectric layers, and a non-conductive via extending through at least a portion of the plurality of dielectric layers to intersect the conductor. A conductive body in an activated state is introduced into the non-conductive via, and upon contacting the conductor, the activated state conductive body adheres to the conductor. The activated state conductive body is then effected to a deactivated state, wherein the conductive body is affixed to the conductor to provide an electrical connection thereto.

Abstract translation: 提供的是具有多个堆叠的电介质层的多层PCB，设置在多个电介质层中的至少一个介质层上的导体，以及延伸穿过多个电介质层的至少一部分的非导电通孔， 与导体相交。 处于激活状态的导电体被引入到非导电通孔中，并且在与导体接触时，活化状态导电体粘附到导体。 然后使激活状态的导电体进入去激活状态，其中导电体固​​定到导体以提供与其的电连接。

公开(公告)号：US20040177997A1

公开(公告)日：2004-09-16

申请号：US10469215

申请日：2004-04-29

Inventor： Hanae Hata ,  Tasao Soga ,  Toshiharu Ishida ,  Kazuma Miura ,  Kanko Ishida

IPC: H05K001/09

CPC classification number: H05K3/3484 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/26 ,  B23K35/262 ,  H01L21/4853 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/11003 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0215 ,  H05K2201/10234 ,  H05K2201/10992 ,  Y02P70/613 ,  Y10T428/12715 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: It is an object of the present invention to provide an electronic device using completely new soldered connection, and more particularly to achieve flip chip bonding on a high temperature side in a temperature hierarchy connection as an alternative method for high Pb containing solder including a large mount of Pb. The object can be achieved by using a configuration in which metallic balls including a single metal, an alloy, a chemical compound or a mixture thereof are connected by Sn or In for pads between a chip and a substrate.

Abstract translation: 本发明的目的是提供一种使用全新的焊接连接的电子器件，更具体地说，涉及在温度分级连接中在高温侧实现倒装芯片接合，作为包含大型载体的高含铅焊料的替代方法 的Pb。 该目的可以通过使用包括单个金属，合金，化合物或其混合物的金属球通过Sn或In连接在芯片和衬底之间的衬垫的构造来实现。