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    INTEGRATED CIRCUITS WITH HYBRID FIXED/CONFIGURABLE CLOCK NETWORKS
    101.
    发明申请
    INTEGRATED CIRCUITS WITH HYBRID FIXED/CONFIGURABLE CLOCK NETWORKS 审中-公开

    公开(公告)号：US20180006653A1

    公开(公告)日：2018-01-04

    申请号：US15197403

    申请日：2016-06-29

    Applicant: Altera Corporation

    Inventor： Kenneth Duong ,  Jung Ko

    IPC: H03K19/177 ,  H03K19/173 ,  G06F1/10 ,  G06F1/08

    CPC classification number: H03K19/1774 ,  G06F1/08 ,  G06F1/10 ,  H03K19/1735 ,  H03K19/1737 ,  H03K19/17744 ,  H03K19/1776

    Abstract: An integrated circuit with a clock distribution network is provided. The clock distribution network may include configurable clock routing paths linking a clock source to one or more clock tree roots and may also include fixed clock routing paths linking the clock tree roots to corresponding leaf nodes. Both the configurable clock routing paths and the fixed clock routing paths can be implemented using an array of logic regions, where each logic region includes a clock switching box, a horizontal routing segment, a vertical routing segment, and associated logic circuitry. The configurable routing paths may include horizontal/vertical routing segments with bidirectional tristate buffers. The fixed routing paths may include horizontal/vertical routing segments with unidirectional inverters that are configured to form an H-tree.

    METHOD AND APPARATUS FOR PHASE-ALIGNED 2X FREQUENCY CLOCK GENERATION
    102.
    发明申请
    METHOD AND APPARATUS FOR PHASE-ALIGNED 2X FREQUENCY CLOCK GENERATION 审中-公开

    公开(公告)号：US20170373675A1

    公开(公告)日：2017-12-28

    申请号：US15195745

    申请日：2016-06-28

    Applicant: ALTERA CORPORATION

    Inventor： Yanjing KE

    IPC: H03K5/15 ,  H03K5/156 ,  H03K19/20 ,  H03M9/00

    CPC classification number: H03K5/15066 ,  H03K5/1565 ,  H03K19/1737 ,  H03K19/17744 ,  H03K19/20 ,  H03M9/00

    Abstract: One embodiment relates to a multiple-channel serializer circuit that includes a plurality of one-channel serializers. A one-channel serializer of the plurality of one-channel serializes includes a local 2× frequency clock generator with a non-divider structure. Other embodiments relate to methods of using a non-divider circuit to generate a local 2× frequency clock signal in a one-channel serializer of a multiple-channel serializer. Another embodiment relates to a local 2× frequency clock generator circuit with a non-divider structure. The local 2× frequency clock generator circuit includes a first circuit path which is selected by multiplexers for a first serialization ratio and may also include a second circuit path which is selected by the multiplexers for a second serialization ratio. Other embodiments and features are also disclosed.

    Wafer-level fan-out wirebond packages
    105.
    发明授权
    Wafer-level fan-out wirebond packages 有权

    公开(公告)号：US09842820B1

    公开(公告)日：2017-12-12

    申请号：US14960180

    申请日：2015-12-04

    Applicant: Altera Corporation

    Inventor： Minghao Shen

    IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

    CPC classification number: H01L24/24 ,  H01L24/19 ,  H01L24/49 ,  H01L24/82 ,  H01L24/85 ,  H01L25/0655 ,  H01L2224/2405 ,  H01L2224/24137

    Abstract: An integrated circuit package that includes an integrated circuit die, a redistribution substrate, a wirebond interconnect and a package substrate is disclosed. The redistribution substrate is formed on the integrated circuit die and may be wider than the integrated circuit die. The package substrate is formed below the integrated circuit die. The wirebond interconnect may have one of its ends attached to the redistribution substrate and another end attached to the package substrate. In addition to that, another integrated circuit die may be formed between the redistribution substrate and the package substrate. The integrated circuit dies may communicate with each other through the redistribution substrate. In addition to that, a method to manufacture the integrated circuit package may also be disclosed.

    LOW-SKEW CHANNEL BONDING USING PHASE-MEASURING FIFO BUFFER
    106.
    发明申请
    LOW-SKEW CHANNEL BONDING USING PHASE-MEASURING FIFO BUFFER 审中-公开

    公开(公告)号：US20170353335A1

    公开(公告)日：2017-12-07

    申请号：US15684310

    申请日：2017-08-23

    Applicant: ALTERA CORPORATION

    Inventor： David W. MENDEL ,  Han Hua LEONG

    IPC: H04L25/14 ,  H04L12/24 ,  H04L12/26 ,  H04L12/875

    CPC classification number: H04L25/14 ,  G06F5/06 ,  H04L41/0896 ,  H04L43/087 ,  H04L47/56

    Abstract: Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.

    INTEGRATED CIRCUIT CALIBRATION SYSTEM USING GENERAL PURPOSE PROCESSORS
    107.
    发明申请
    INTEGRATED CIRCUIT CALIBRATION SYSTEM USING GENERAL PURPOSE PROCESSORS 审中-公开

    公开(公告)号：US20170350937A1

    公开(公告)日：2017-12-07

    申请号：US15685516

    申请日：2017-08-24

    Applicant: Altera Corporation

    Inventor： Wai Tat Wong ,  Edwin Yew Fatt Kok ,  Wilfred Wee Kee King ,  Tee Wee Tan

    IPC: G01R31/28

    CPC classification number: G01R31/2851 ,  H03K19/17764

    Abstract: In one embodiment, an integrated circuit is disclosed. The integrated includes a general purpose processor, an interface circuit, and a calibration adapter circuit. The general purpose processor circuit generates calibration test inputs based on user instruction. The analog interface circuit may include a calibration bus circuit. The calibration bus circuit may receive the calibration test input from the general purpose processor circuit. The calibration adapter circuit is coupled to the calibration bus circuit and the general purpose processor circuit and transmits the calibration test inputs to the calibration bus circuit.

    Address arithmetic on block RAMs
    108.
    发明授权
    Address arithmetic on block RAMs 有权

    公开(公告)号：US09837133B1

    公开(公告)日：2017-12-05

    申请号：US15177088

    申请日：2016-06-08

    Applicant: Altera Corporation

    Inventor： Bruce B. Pedersen

    IPC: G06F12/06 ,  G11C7/10

    CPC classification number: G11C7/1072 ,  G06F12/06 ,  G11C7/10 ,  G11C7/1036 ,  G11C8/04 ,  G11C8/06 ,  G11C8/18

    Abstract: Systems and methods are disclosed for reducing or eliminating address lines that need to be routed to multiple related embedded memory blocks. In particular, one or more inputs are added to a block RAM such that when one or more of the inputs are asserted, the address input to the Block RAM may be incremented prior to being used to retrieve data contents of the block RAM. Thus, if address is provided to the block RAM and the address increment signal is asserted, data may be read from location instead of , where N may be an integer. Block RAMs with such address arithmetic may be used to implement wide First-In-First-Out (FIFO) queues, wide memories, and/or data-burst accessible block RAMs.

    EMBEDDED BUILT-IN SELF-TEST (BIST) CIRCUITRY FOR DIGITAL SIGNAL PROCESSOR (DSP) VALIDATION
    110.
    发明申请
    EMBEDDED BUILT-IN SELF-TEST (BIST) CIRCUITRY FOR DIGITAL SIGNAL PROCESSOR (DSP) VALIDATION 审中-公开

    公开(公告)号：US20170328951A1

    公开(公告)日：2017-11-16

    申请号：US15154266

    申请日：2016-05-13

    Applicant: Altera Corporation

    Inventor： Weng Hong Liew

    IPC: G01R31/3177 ,  G11C8/04

    CPC classification number: G01R31/3177 ,  G01R31/3187 ,  G11C8/04

    Abstract: Programmable integrated circuits with specialized processing blocks such as digital signal processing (DSP) blocks are provided. Each DSP block may include embedded built-in self-test circuitry implemented using existing input registers and output registers in the DSP blocks. The input registers may be selectively coupled in a loop to serve as a linear feedback shift register (LFSR). The output registers may be selectively coupled in a chain to serve as a multiple input signature register (MISR).Configured in this way, the LIFR and the MISR circuits of the DSP blocks are not implemented using soft logic and can therefore easily meet performance criteria.

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