公开(公告)号：US11152290B2

公开(公告)日：2021-10-19

申请号：US16094817

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Van H. Le ,  Willy Rachmady ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L23/498 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

Abstract: A subfin layer is deposited on a substrate. A fin layer is deposited on the subfin layer. The subfin layer has a conduction band energy offset relative to the fin layer to prevent a leakage in the subfin layer. In one embodiment, the subfin layer comprises a group IV semiconductor material layer that has a bandgap greater than a bandgap of the fin layer.

公开(公告)号：US11145737B2

公开(公告)日：2021-10-12

申请号：US16642254

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Van H. Le ,  Gilbert W. Dewey ,  Willy Rachmady

IPC: H01L27/24 ,  H01L29/47 ,  H01L27/22 ,  H01L29/861 ,  H01L29/872 ,  H01L29/24

Abstract: Disclosed herein are selector devices, and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, a selector material between the first electrode and the second electrode, and a getter layer between the first electrode and the selector material. The first electrode may include a material having a work function that is less than 4.5 electron volts.

公开(公告)号：US11101377B2

公开(公告)日：2021-08-24

申请号：US15939087

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Gilbert Dewey ,  Van H. Le ,  Willy Rachmady ,  Ravi Pillarisetty

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/267

Abstract: Techniques and mechanisms for providing efficient transistor functionality of an integrated circuit. In an embodiment, a transistor device comprises a first body of a high mobility semiconductor and a second body of a wide bandgap semiconductor. The first body adjoins each of, and is disposed between, the second body and a gate dielectric layer of the transistor. The second body extends between, and variously adjoins, each of a source of the transistor and a drain of the transistor. A location of the second body mitigates current leakage that might otherwise occur via the first body. In another embodiment, a mobility of the first body is equal to or greater than 100 cm2/V·s, wherein a bandgap of the second body is equal to or greater than 2.0 eV.

公开(公告)号：US11081483B2

公开(公告)日：2021-08-03

申请号：US16637592

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Ravi Pillarisetty ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Van H. Le

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/786 ,  H01L21/8252 ,  H01L29/66

Abstract: Techniques and mechanisms for providing a complementary metal-oxide-semiconductor (CMOS) circuit which includes a group III-nitride (III-N) material. In an embodiment, an n-type transistor of the CMOS circuit comprises structures which are variously disposed on a group III-N semiconductor material. The n-type transistor is coupled to a p-type transistor of the CMOS circuit, wherein a channel region of the p-type transistor comprises a group III-V semiconductor material. The channel region is configured to conduct current along a first direction, where a surface portion of the group III-N semiconductor material extends along a second direction perpendicular to the second direction. In another embodiment, the group III-N semiconductor material includes a gallium-nitride (GaN) compound, and the group III-V semiconductor material includes a nanopillar of an indium antimonide (InSb) compound.

公开(公告)号：US11075202B2

公开(公告)日：2021-07-27

申请号：US16650155

申请日：2018-01-10

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Gilbert Dewey ,  Willy Rachmady ,  Patrick Morrow ,  Rishabh Mehandru

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: An integrated circuit structure includes a first portion of a bottom semiconductor fin extending horizontally in a length direction and vertically in a height direction, a second portion of the bottom semiconductor fin extending horizontally in the length direction and vertically in the height direction, a top semiconductor fin extending horizontally in the length direction and vertically in the height direction, and an insulator region extending horizontally in the length direction to electrically insulate the first portion of the bottom semiconductor fin from the second portion of the bottom semiconductor fin. The insulator region further extends vertically in the height direction in vertical alignment with the top semiconductor fin. The insulator region includes at least one of an insulator material and an airgap. In an embodiment, the top semiconductor fin is associated with a transistor, and the insulator region is in vertical alignment with a gate electrode of the transistor.

公开(公告)号：US11017843B2

公开(公告)日：2021-05-25

申请号：US16457617

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Gilbert Dewey ,  Willy Rachmady ,  Van Le ,  Matthew Metz ,  Jack Kavalieros

IPC: G11C11/24 ,  G11C11/4091 ,  H01L27/108 ,  H01L27/12 ,  G11C11/4094 ,  G11C11/408

Abstract: In memory devices where a memory cell includes a thin film cell select transistor, selection between layers of such memory cells may further comprise another thin film select transistor. Bitline and wordline encoding suitable for a memory device having a single layer of memory cells may be scaled up to a 3D memory device having two or more memory cell layers. In a DRAM device one layer of (1TFT-1C) cells may include a 2D array of metal-insulator-metal capacitors over an array of TFTs. Additional layers of such 1TFT-1C cells may be stacked monolithically to form a 3D array. Memory cells in each layer may be accessed through a wordline and local bitline. A local bitline of one cell layer may be coupled to global bitline applicable to all cell layers through a layer-selected TFT according to a voltage applied to a layer-select gate voltage.

公开(公告)号：US20210074702A1

公开(公告)日：2021-03-11

申请号：US16642356

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Van H. Le ,  Marko Radosavljevic ,  Han Wui Then ,  Willy Rachmady ,  Ravi Pillarisetty ,  Abhishek Sharma ,  Gilbert Dewey ,  Sansaptak Dasgupta

IPC: H01L27/092 ,  H01L27/088 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8258

Abstract: A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.

公开(公告)号：US10886408B2

公开(公告)日：2021-01-05

申请号：US16327206

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Chandra S. Mohapatra ,  Harold W. Kennel ,  Glenn A. Glass ,  Willy Rachmady ,  Anand S. Murthy ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Tahir Ghani ,  Matthew V. Metz ,  Sean T. Ma

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/66 ,  H01L29/20 ,  H01L27/092 ,  H01L29/786 ,  H01L29/10 ,  H01L29/26 ,  H01L21/8252 ,  H01L29/16

Abstract: Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.5 percent.

公开(公告)号：US20200335610A1

公开(公告)日：2020-10-22

申请号：US16957667

申请日：2018-02-28

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US10804357B2

公开(公告)日：2020-10-13

申请号：US16740132

申请日：2020-01-10

Applicant: Intel Corporation

Inventor： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/306 ,  H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  B82Y40/00

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.