Abstract:
Attempts to update confirmation information or firmware for a hardware device can be monitored using a secure counter that is configured to monotonically adjust a current value of the secure counter for each update or update attempt. The value of the counter can be determined every time the validity of the firmware is confirmed, and this value can be stored to a secure location. At subsequent times, such as during a boot process, the actual value of the counter can be determined and compared with the expected value. If the values do not match, such that the firmware may be in an unexpected state, an action can be taken, such as to prevent access to, or isolate, the hardware until such time as the firmware can be validated or updated to an expected state.
Abstract:
A computer system for determining whether or not a tool for deploying a software patch should be invoked is provided. The system may include a receiver that receives information regarding patch deployment over a first pre-determined amount of time. The system may include a processor configured to determine, based on the historical information, a patch deployment index. The patch deployment index may characterize patch deployment as a number of patches deployed per unit time. The receiver may receive historical information regarding patch deployment over a second amount of time. The processor may use the historical information regarding patch deployment of the second pre-determined amount of time to determine a second patch deployment index. The processor may compare the first deployment to the second patch deployment index. When the difference between the second index and the first index is greater than a pre-determined threshold, the processor may invoke the tool.
Abstract:
A device for supporting hardware enabled performance counters with support for context switching include a plurality of performance counters operable to collect information associated with one or more computer system related activities, a first register operable to store a memory address, a second register operable to store a mode indication, and a state machine operable to read the second register and cause the plurality of performance counters to copy the information to memory area indicated by the memory address based on the mode indication.
Abstract:
Technology for operating a cache sizing system is disclosed. In various embodiments, the technology monitors input/output (IO) accesses to a storage system within a monitor period; tracks an access map for storage addresses within the storage system during the monitor period; and counts a particular access condition of the IO accesses based on the access map during the monitor period. When sizing a cache of the storage system that enables the storage system to provide a specified level of service, the counting is for computing a working set size (WSS) estimate of the storage system.
Abstract:
A common action flow for an application is identified by processing session data maintained for a plurality of users to identify a plurality of action flows. Each action flow represents a series of actions taken by one of the users navigating the application's user interface during a session. A data structure is generated from the plurality of action flows. That data structure is indicative of a plurality of candidate sub-flows. The data structure is analyzed to identify a selected one of the candidate sub-flows repeated in multiple ones of the plurality of action flows. That identified sub-flow is the common action flow. Data representative of the identified common action flow can then be communicated.
Abstract:
Methods, computer-readable mediums and systems for reducing transistor recovery are disclosed. Data which toggles at least one bit may be periodically communicated over a data path, where toggling of at least one bit may effectively reset the recovery period for any transistors in the data path associated with the at least one bit. Timing uncertainty associated with a given transistor may be reduced by limiting the amount of recovery experienced by the transistor. Accordingly, recovery of transistors in a data path may be limited to predetermined amount by toggling bits of the data path at a predetermined frequency, thereby reducing timing uncertainty and allowing a smaller system margin and/or higher data transmission speeds.
Abstract:
A method performed by a computer system, the method including maintaining a plurality of work-based counters, each of the work-based counters being associated with a respective functional entity of a plurality of functional entities, in response to determining that a first one of the work-based counters has reached a threshold, sampling a performance data of a first functional entity associated with the first one of the work-based counters, and presenting the sampled performance data to an analysis tool separate from an operating system of the computer system.
Abstract:
A crawler program collects and stores application programs including application binaries and associated metadata from any number of sources such as official application marketplaces and alternative application marketplaces. An analysis including comparisons and correlations are performed among the collected data in order to detect and warn users about pirated or maliciously modified applications.
Abstract:
Computer-implemented methods, computer program products, and systems are disclosed for tracking content use, the content including textual content that is displayable using RSVP. A particular embodiment identifies content, including textual content, to be displayed using RSVP on an electronic device to a user, displays that content to the user using RSVP, and generates content tracking information by tracking information items of the textual content that are displayed using RSVP. In some embodiments, analysis of what information items have been presented to the user and when is used in combination with analysis of information content items in candidate content items to affect rankings of those candidate content items to be potentially presented to a user in response to a search request or other user interface action received from a user device.
Abstract:
According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile semiconductor memory device includes a memory cell array having a plurality of blocks each including a plurality of memory cells, and a voltage generation unit configured to change a read level of the memory cell. The control unit controls write, read, and erase of the nonvolatile semiconductor memory device. The control unit changes the read level between a start of use of the nonvolatile semiconductor memory device and a timing after an elapse of a time.