公开(公告)号：US20020102495A1

公开(公告)日：2002-08-01

申请号：US10044065

申请日：2002-01-10

Inventor： Kaoru Ohba ,  Hideki Akimoto ,  Brian Martin ,  Albert Charles Marie Achen ,  Philip E. Garrou ,  Ying-Hung So ,  Britton Lee Kaliszewski

IPC: G03F007/004

CPC classification number: H05K3/4655 ,  C08G61/02 ,  H05K3/4652 ,  H05K2201/0158 ,  H05K2201/0358

Abstract: The invention is a process for building-up printed wiring boards using metal foil coated with toughened benzocyclobutene-based dielectric polymers. The invention is also a toughened dielectric polymer comprising benzocyclobutene-based monomers or oligomers, ethylenically unsaturated polymer additive, and, optionally, a photoactive compound.

公开(公告)号：US20020074158A1

公开(公告)日：2002-06-20

申请号：US10020590

申请日：2001-12-13

Inventor： Michael E. St. Lawrence ,  Scott D. Kennedy

IPC: B32B015/00

CPC classification number: H05K3/4655 ,  H05K3/4652 ,  H05K2201/0141 ,  H05K2201/0195 ,  H05K2201/0358 ,  Y10T428/24917 ,  Y10T428/2495

Abstract: A multi-layer circuit comprises a circuit and a resin covered conductive layer disposed on the circuit, wherein the resin covered conductive layer comprises a liquid crystalline polymer resin laminated to a conductive layer. Such multi-layer circuits are particularly useful for high density circuit applications.

Abstract translation: 多层电路包括设置在电路上的电路和树脂覆盖的导电层，其中树脂覆盖的导电层包括层压到导电层的液晶聚合物树脂。 这种多层电路对于高密度电路应用特别有用。

公开(公告)号：US06405431B1

公开(公告)日：2002-06-18

申请号：US09467780

申请日：1999-12-20

Applicant: Dong Shin ,  Keon Yang Park ,  Young Hwan Shin ,  Byung Kook Sun ,  Jae Heun Joung

Inventor： Dong Shin ,  Keon Yang Park ,  Young Hwan Shin ,  Byung Kook Sun ,  Jae Heun Joung

IPC: H01K310

CPC classification number: H05K3/4652 ,  H05K3/0035 ,  H05K3/0038 ,  H05K2201/0358 ,  H05K2201/09518 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for manufacturing a build-up multi-layer printed circuit board is disclosed in which a YAG laser is used upon the formation of a via hole in the multi-layer printed circuit board, such that it can have the following advantages: the manufacturing process would become simple; the component packaging density and freedom for the design of the board would be improved; and a high speed of signal process would be ensured. The method for manufacturing a build-up multi-layer printed circuit board includes the steps of: forming a first printed circuit pattern on a copper clad laminate (CCL) by applying a general photo-etching process, the CCL having a copper foil on the one face thereof; stacking a resin-coated (on one face) copper foil (RCC) on the CCL with the first printed circuit pattern formed thereon, and heating and pressing this structure; irradiating a YAG laser to the board with said RCC stacked so as to form a via hole at a predetermined position by removing said RCC; carrying out an electroless and electro copper plating on the board with the via hole formed therein to form a plated layer; and forming a second printed circuit pattern on said plated layer to electrically connect the layers on which the first and second printed circuit patterns are formed.

Abstract translation: 公开了一种用于制造积层多层印刷电路板的方法，其中在多层印刷电路板中形成通孔时使用YAG激光器，使得其可以具有以下优点：制造 过程变得简单; 组件封装密度和板的设计自由度将得到改善; 并且可以确保信号处理的高速度。 用于制造积层多层印刷电路板的方法包括以下步骤：通过施加一般的光蚀刻工艺在覆铜层压板（CCL）上形成第一印刷电路图案，将具有铜箔的CCL 一面; 在其上形成有第一印刷电路图案的CCL上堆叠树脂涂覆（一面）铜箔（RCC），并加热并压制该结构; 用所述RCC将YAG激光照射到所述板上，以便通过去除所述RCC在预定位置形成通孔; 在其上形成有通孔的板上进行化学镀和电镀铜以形成镀层; 以及在所述镀层上形成第二印刷电路图案，以电连接形成有第一和第二印刷电路图案的层。

公开(公告)号：US20010042637A1

公开(公告)日：2001-11-22

申请号：US09797916

申请日：2001-03-05

Inventor： Naohiro Hirose ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

IPC: H05K001/03

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 nullm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Abstract translation: 通过激光束在树脂20中形成开口，从而形成通孔。 此时，通过进行蚀刻来降低导热率的铜箔22的厚度（3μm）被用作保形掩模。 因此，如果脉冲形激光束的照射次数减少，则可以在树脂20中形成开口20a。 因此，可以防止形成层间绝缘树脂层的树脂20的底切的发生。 因此，可以提高通孔连接的可靠性。

公开(公告)号：US20010039729A1

公开(公告)日：2001-11-15

申请号：US09909021

申请日：2001-07-19

Inventor： Benjamin B. Ross ,  Phillip L. Jordan ,  Jeffery A. Strole

IPC: H05K003/30 ,  H01K003/10

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0269 ,  H05K1/112 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/0082 ,  H05K3/4652 ,  H05K2201/0358 ,  H05K2201/09227 ,  H05K2201/09918 ,  H05K2201/10734 ,  H05K2203/107 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49213 ,  Y10T29/5313 ,  H01L2924/00

Abstract: A method of constructing an electric apparatus, comprising the following steps. First, a set of dielectric layers is provided. Next, a set of conductive features and at least one fiducial marking are formed on a first one of the dielectric layers, in mutual reference to each other so that their relative positions are known to a first tolerance. Then, a set of pin holes is formed in each dielectric layer, each pin hole formed in relation to the fiducial marking for its dielectric layer and all of the sets of pin holes having a mutually identical placement. Finally the dielectric layers are arranged onto a pin fixture having a set of pins that match the mutually identical placement of the pin holes.

Abstract translation: 一种构成电气设备的方法，包括以下步骤。 首先，提供一组电介质层。 接下来，一组导电特征和至少一个基准标记形成在彼此相互参考的第一介电层上，使得它们的相对位置已知为第一公差。 然后，在每个电介质层中形成一组销孔，每个针孔相对于其电介质层的基准标记形成，并且所有这些销孔组具有相互相同的位置。 最后，电介质层布置在具有匹配销孔相互相同位置的一组销的销钉固定件上。

公开(公告)号：US20010018986A1

公开(公告)日：2001-09-06

申请号：US09788465

申请日：2001-02-21

Inventor： Akira Nagai ,  Masayuki Noda

IPC: H05K001/02

CPC classification number: H05K3/4655 ,  C08L33/00 ,  C08L79/08 ,  C08L2666/02 ,  C09J7/10 ,  C09J179/08 ,  C09J2433/00 ,  C09J2479/08 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0154 ,  H05K2201/0358 ,  Y10T428/24917 ,  H01L2924/00

Abstract: The present invention provides a resin compound, which causes very little thermal stress even when a flip chip is mounted, is of low elastic modulus, and has high heat resistance enough for solder floating at 300null C., and also an adhesive film, metal-clad adhesive film, circuit board, and assembly structure using the resin compound. The present invention is a resin compound containing (A) polyamide imide with siloxane bond, (B) acrylic polymer with weight-average molecular weight of 500,000 or more, (C) thermoset resin, and (D) solvent; an adhesive film and a metal-clad adhesive film using the resin compound; and also a circuit board and an assembly structure made with these films.

Abstract translation: 本发明提供一种树脂化合物，即使安装倒装芯片也导致极少的热应力，其弹性模量低，并且具有足够高的耐热性，足以在300℃下漂浮，还有粘合剂膜，金属 - 使用该树脂化合物的粘合膜，电路板和组装结构。 本发明是含有（A）具有硅氧烷键的聚酰胺酰亚胺，（B）重均分子量为500,000以上的丙烯酸类聚合物，（C）热固性树脂和（D）溶剂）的树脂化合物， 粘合剂膜和使用该树脂化合物的金属包覆粘合膜; 以及由这些膜制成的电路板和组装结构。

公开(公告)号：US6153359A

公开(公告)日：2000-11-28

申请号：US275874

申请日：1999-03-25

Applicant: Hiroshi Shimizu ,  Nobuyuki Ogawa ,  Katsuji Shibata ,  Akishi Nakaso

Inventor： Hiroshi Shimizu ,  Nobuyuki Ogawa ,  Katsuji Shibata ,  Akishi Nakaso

IPC: C08J7/12 ,  H05K3/46 ,  H01L21/306 ,  B23F1/018 ,  C23C3/002

CPC classification number: C08J7/12 ,  C08J2363/00 ,  H05K2201/0358 ,  H05K2203/0554 ,  H05K2203/0783 ,  H05K3/4652

Abstract: An etching solution comprising (A) an amine as a solvent, (B) an alkali metal compound, and (C) an alcohol as a solvent, this etching solution being a non-aqueous solution. This etching solution is-effective for etching a cured epoxy resin layer for forming holes for interstitial via holes having a small diameter, in the production of a multilayer printed circuit board. This etching solution is particularly effective for etching a cured epoxy resin layer formed from a thermosetting epoxy resin composition including (a) an epoxy resin, (b) a crosslinking agent, and (c) a polyfunctional epoxy resin, which forms a thermosetting copper-clad adhesive resin sheet which covers an interlayer circuit plate of a multilayer printed circuit board.

Abstract translation: 一种蚀刻溶液，其包含（A）作为溶剂的胺，（B）碱金属化合物和（C）醇作为溶剂，该蚀刻溶液是非水溶液。 在多层印刷电路板的制造中，该蚀刻溶液对于蚀刻用于形成具有小直径的间隙通孔的孔的固化环氧树脂层是有效的。 该蚀刻溶液对于蚀刻由包含（a）环氧树脂，（b）交联剂和（c）多官能环氧树脂的热固性环氧树脂组合物形成的固化环氧树脂层是特别有效的， 覆盖多层印刷电路板的层间电路板的复合粘合树脂片。

公开(公告)号：US6119335A

公开(公告)日：2000-09-19

申请号：US203489

申请日：1998-12-02

Applicant: Keon Yang Park ,  Byung Kook Sun ,  Jae Heun Joung ,  Dong Shin

Inventor： Keon Yang Park ,  Byung Kook Sun ,  Jae Heun Joung ,  Dong Shin

IPC: H05K3/00 ,  H05K3/46 ,  H05K3/36

CPC classification number: H05K3/0038 ,  H05K3/4652 ,  H05K2201/0358 ,  H05K2203/108 ,  H05K3/0035 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A method for manufacturing a build-up multi-layer printed circuit board for use in computers, VTR, or portable telephones is disclosed, in which the method of forming a hole in a circuit layer and the method of forming a hole in an insulating layer are made different from each other by applying a combined formation method, thereby improving the formation precision and efficiency in forming the holes. Specifically, a resin-clad copper foil (RCC) is stacked on a CCL (copper-clad laminate) after forming a printed circuit layer, and this structure is heated and pressed. Then, beams of an Nd-YAG laser are irradiated to remove the copper-clad layer, and then beams of CO.sub.2 laser are irradiated to remove the residual resin insulator, thereby forming a via hole. Then, circuit patterns are formed on the board on which the via hole has been formed.

Abstract translation: 公开了一种制造用于计算机，VTR或便携式电话的积层多层印刷电路板的方法，其中在电路层中形成孔的方法和在绝缘层中形成孔的方法 通过组合形成方法彼此不同，从而提高了形成孔的形成精度和效率。 具体地，在形成印刷电路层之后，在CCL（覆铜层压板）上堆叠树脂包覆铜箔（RCC），并且对该结构进行加热和加压。 然后，照射Nd-YAG激光的光束以除去覆铜层，然后照射二氧化碳激光束以除去残留的树脂绝缘体，从而形成通孔。 然后，在已经形成通孔的板上形成电路图案。

公开(公告)号：US5800722A

公开(公告)日：1998-09-01

申请号：US640491

申请日：1996-05-01

Applicant: Hiroaki Tsuyoshi ,  Tetsuro Sato

Inventor： Hiroaki Tsuyoshi ,  Tetsuro Sato

IPC: H05K1/03 ,  C09J163/00 ,  H05K3/38 ,  H05K3/46 ,  B44C1/22

CPC classification number: H05K3/4655 ,  H05K3/385 ,  H05K2201/0133 ,  H05K2201/0358 ,  H05K2203/0315 ,  H05K3/4652

Abstract: A multilayer printed wiring board wherein an inner-layer copper circuit is provided on one or both of the surfaces of an inner-layer substrate, and subsequent copper circuit is cumulatively provided through an insulating layer on the outside of the inner-layer copper circuit, characterized in that the inner-layer copper circuit has a cuprous oxide film formed on the surface thereof the insulating layer which remarkably facilitate the interlayer adhesion between the inner-layer copper circuit. This multilayer printed wiring board has high interlayer adhesiveness and moistureproofness without causing any haloing phenomena when soaked with an acidic solution.

Abstract translation: 在内层基板的一面或两面上设置有内层铜电路的多层印刷电路板，通过内层铜电路外侧的绝缘层累积设置后续的铜电路， 其特征在于，内层铜电路在其表面上形成有氧化亚铜膜，该绝缘层显着促进了内层铜电路之间的层间粘附。 该多层印刷线路板具有高的层间粘合性和防潮性，而在酸性溶液浸渍时不产生任何晕圈现象。

公开(公告)号：US5718039A

公开(公告)日：1998-02-17

申请号：US516480

申请日：1995-08-17

Applicant: Muneo Saida ,  Muneharu Ohara ,  Teturoh Satoh

Inventor： Muneo Saida ,  Muneharu Ohara ,  Teturoh Satoh

IPC: H05K1/03 ,  C09J163/00 ,  H05K3/46 ,  H05K3/02

CPC classification number: H05K3/4655 ,  H05K2201/0133 ,  H05K2201/0355 ,  H05K2201/0358 ,  H05K3/4652 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T428/2804

Abstract: A process for preparing said multilayer printed wiring board comprising the steps of (1) adhering copper foils respectively to both the faces of a substrate, masking and etching said foils in a usual way to form circuits, (2) applying copper foils having a semi-cured insulating layer formed on one face thereof respectively to said circuits with the insulating layer facing to said circuit, the insulating layers being as defined above, and then pressing the whole together under heat and (3) masking and etching the copper foils with the insulating layer thereon in a usual way to form circuits, the steps (2) and (3) being repeated as many times as desired.

Abstract translation: 一种制备所述多层印刷线路板的方法，包括以下步骤：（1）将铜箔分别粘附到基片的两个表面上，以常规方法掩蔽和蚀刻所述箔以形成电路;（2）施加具有半 绝缘层分别形成在其一面上的绝缘层面向所述电路的绝缘层，绝缘层如上所述，然后在加热下将其全部压在一起，（3）用铜箔掩模和蚀刻铜箔 以通常的方式在其上形成绝缘层以形成电路，步骤（2）和（3）根据需要重复多次。