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    Method for measuring film thickness distribution of wafer with thin films
    111.
    发明授权
    Method for measuring film thickness distribution of wafer with thin films 有权

    公开(公告)号：US11965730B2

    公开(公告)日：2024-04-23

    申请号：US17762859

    申请日：2020-09-16

    Applicant: SHIN-ETSU HANDOTAI CO., LTD. ,  UNITY SEMICONDUCTOR

    Inventor： Susumu Kuwabara ,  Kevin Quinquinet ,  Philippe Gastaldo

    IPC: G01B11/06

    CPC classification number: G01B11/0625

    Abstract: A method includes: determining height Z1 of a focus by an optical microscope having autofocus function which uses irradiation light of wavelength λ0 to adjust the focus; determining a wavelength λ1 of irradiation light used for obtaining observation image of second thin film; obtaining observation image of second thin film by using irradiation light of the wavelength λ1, while altering heights of the focus with the Z1 as reference point; calculating standard deviation of reflected-light intensity distribution within the observation image, obtaining height Z2 of the focus corresponding to a peak position where standard deviation is greatest, and calculating a difference ΔZ between Z1 and Z2; correcting the autofocus function with ΔZ as a correction value; and using the corrected autofocus function to adjust the focus, obtaining the observation image of the second thin film, and calculating the film thickness distribution from the reflected-light intensity distribution within the observation image.

    Method and system for optically inspecting a substrate
    116.
    发明授权
    Method and system for optically inspecting a substrate 有权

    公开(公告)号：US11300520B2

    公开(公告)日：2022-04-12

    申请号：US16959930

    申请日：2018-12-27

    Applicant: UNITY SEMICONDUCTOR

    Inventor： Mayeul Durand De Gevigney

    IPC: G01N21/88 ,  G01N21/95

    Abstract: A method and related system for substrate inspection, includes: creating, based on two light beams originating from one light source, a measurement volume at the intersection between the two light beams, the measurement volume containing interference fringes and being positioned to extend into the substrate, the substrate moving relative to the measurement volume in a direction parallel to a main surface S of the substrate; acquiring a measurement signal representative of the light scattered by the substrate, as a function of the location of the measurement volume on the substrate; calculating at least one expected modulation frequency, of an expected signal representative of the passage of a defect of the substrate through the measurement volume; determining values representative of a frequency content of the measurement signal close to the modulation frequency, to constitute a validated signal representative of the presence of defects; and analyzing the signal to locate and/or identify defects.

    METHOD AND SYSTEM FOR MEASURING A SURFACE OF AN OBJECT COMPRISING DIFFERENT STRUCTURES USING LOW COHERENCE INTERFEROMETRY
    117.
    发明申请
    METHOD AND SYSTEM FOR MEASURING A SURFACE OF AN OBJECT COMPRISING DIFFERENT STRUCTURES USING LOW COHERENCE INTERFEROMETRY 有权

    公开(公告)号：US20220011088A1

    公开(公告)日：2022-01-13

    申请号：US17296117

    申请日：2019-11-28

    Applicant: UNITY SEMICONDUCTOR

    Inventor： Jean-François BOULANGER ,  Isabelle BERGOËND

    IPC: G01B9/02 ,  G01B11/06

    Abstract: A method for measuring a surface of an object including at least one structure using low coherence optical interferometry, the method including the following steps: acquiring an interferometric signal at a plurality of points, called measurement points, of the surface in a field of view; for at least one measurement point: attributing the interferometric signal acquired to a class of interferometric signals from a plurality of classes, each class being associated with a reference interferometric signal representative of a typical structure; and analysing the interferometric signal to derive therefrom an item of information on the structure at the measurement point, as a function of its class. A measuring system implementing the present method is also provided.

    Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations
    118.
    发明授权
    Global bit line pre-charge circuit that compensates for process, operating voltage, and temperature variations 有权

    公开(公告)号：US11087841B2

    公开(公告)日：2021-08-10

    申请号：US16784332

    申请日：2020-02-07

    Applicant: Unity Semiconductor Corporation

    Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

    IPC: G11C11/00 ,  G11C13/00 ,  G11C7/04 ,  G11C7/00 ,  G11C16/24 ,  G11C7/12 ,  G11C5/08 ,  G11C7/18 ,  G11C5/06 ,  H01L27/10

    Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

    Preservation circuit and methods to maintain values representing data in one or more layers of memory
    119.
    发明授权
    Preservation circuit and methods to maintain values representing data in one or more layers of memory 有权

    公开(公告)号：US10971227B2

    公开(公告)日：2021-04-06

    申请号：US16657329

    申请日：2019-10-18

    Applicant: Unity Semiconductor Corporation

    Inventor： Christophe Chevallier ,  Robert Norman

    IPC: G11C13/00 ,  G11C5/02 ,  G11C11/16 ,  G11C5/00

    Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

    CONDUCTIVE METAL OXIDE STRUCTURES IN NON-VOLATILE RE-WRITABLE MEMORY DEVICES
    120.
    发明申请
    CONDUCTIVE METAL OXIDE STRUCTURES IN NON-VOLATILE RE-WRITABLE MEMORY DEVICES 有权

    公开(公告)号：US20210098063A1

    公开(公告)日：2021-04-01

    申请号：US17066198

    申请日：2020-10-08

    Applicant: Unity Semiconductor Corporation

    Inventor： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Rene Meyer

    IPC: G11C13/00 ,  G11C11/56 ,  H01L27/24 ,  H01L45/00

    Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

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