公开(公告)号：US06360431B1

公开(公告)日：2002-03-26

申请号：US09853279

申请日：2001-05-11

Applicant: Joe A. Harrison ,  Edward R. Stanford ,  Thomas G. Ruttan

Inventor： Joe A. Harrison ,  Edward R. Stanford ,  Thomas G. Ruttan

IPC: H05K330

CPC classification number: H05K1/141 ,  G06F1/189 ,  H05K1/0263 ,  H05K3/325 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09345 ,  H05K2201/10325 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A system for delivering power to a processor enables a DC-to-DC converter substrate to be secured to the processor carrier in the Z-axis direction. The ability to assemble the converter to the processor in this way facilitates assembly compared to systems in which the converter is plugged in to the processor carrier in the direction substantially parallel to the surface of the motherboard.

公开(公告)号：US06351391B1

公开(公告)日：2002-02-26

申请号：US09571956

申请日：2000-05-15

Applicant: Clint A. Beliveau ,  Wallace D. Doeling

Inventor： Clint A. Beliveau ,  Wallace D. Doeling

IPC: H05K710

CPC classification number: H05K1/167 ,  H01L23/647 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0298 ,  H05K1/141 ,  H05K2201/049 ,  H05K2201/10734 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A printed circuit board structure is provided where there is a circuitized dielectric substrate having a plurality of signal traces thereon. The circuitized substrate has first and second opposite faces. An ASIC chip assembly is mounted on the first face and connected to the surface by solder connections. Preferably, the ASIC chip assembly is mounted on the substrate as an IC chip mounted on a chip carrier with the chip carrier being mounted to the circuit board by solder connections, preferably in the form of a ball grid array. In one embodiment, a discrete signal termination device is provided which is disposed on the second face of the circuitized substrate directly opposite the ASIC chip assembly. In another embodiment, a discrete signal termination device is disposed between the ASIC chip assembly and the printed circuit board. The signal termination device includes a plurality of planar resistors embedded in a dielectric material with the resistors being electrically connected to the signal lines on the circuitized substrate, preferably by solder connections, again in the form of a ball grid array. In yet another embodiment, the signal termination device is formed as a part of the ASIC chip assembly by being incorporated in the chip carrier In all cases, the signal termination device need not be formed as a part of the circuit board but can be formed in discrete individual segments for attachment to either the circuit board or formed as part of the chip carrier, thus utilizing the entire structure of the termination device to form resistors.

Abstract translation: 提供了一种印刷电路板结构，其中存在其上具有多个信号迹线的电路化电介质基板。 电路化基板具有第一和第二相对面。 ASIC芯片组件安装在第一面上，并通过焊接连接连接到表面。 优选地，ASIC芯片组件作为安装在芯片载体上的IC芯片安装在基板上，其中芯片载体通过焊接连接安装到电路板，优选地以球栅阵列的形式。在一个实施例中，离散 提供信号终端装置，其设置在与ASIC芯片组件正对的电路化基板的第二面上。 在另一个实施例中，离散信号终端装置设置在ASIC芯片组件和印刷电路板之间。信号终端装置包括嵌入电介质材料中的多个平面电阻器，其中电阻器电连接到电路化的 衬底，优选地通过焊料连接，再次以球栅阵列的形式。在另一个实施例中，信号终端装置通过结合在芯片载体中而形成为ASIC芯片组件的一部分。在所有情况下，信号终端装置 不需要形成为电路板的一部分，而是可以形成在离散的各个片段中，用于附接到电路板或形成为芯片载体的一部分，从而利用终端装置的整个结构来形成电阻器。

公开(公告)号：US06344684B1

公开(公告)日：2002-02-05

申请号：US09610865

申请日：2000-07-06

Applicant: Rafiqul Hussain ,  Phuc Dinh Do ,  Benjamin G. Tubera

Inventor： Rafiqul Hussain ,  Phuc Dinh Do ,  Benjamin G. Tubera

IPC: H01L2348

CPC classification number: H05K1/141 ,  G01R1/0483 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/325 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/10325 ,  H05K2201/10704 ,  H05K2201/10734

Abstract: A multi-layered pin grid array interposer used in a test socket for testing and converting a package having a non-pin grid array footprint to a pin grid array footprint. The multi-layered pin grid array interposer test socket includes a multi-layered pin grid array interposer, a semiconductor device mounted on a package having a non-grid array footprint and a fastener. The multi-layered pin grid array interposer includes a top signal layer having bonding pads on an upper surface, a bottom signal layer having a pin grid array footprint on a bottom surface, at least one power layer between ground layers, the ground layers being between the top signal layer and bottom signal layer, and a links for connecting the plurality of bonding pads to the pins of the pin grid array footprint. The fastener presses the package against the multi-layered pin grid array interposer connecting the leads of the package with the bonding pads.

Abstract translation: 用于测试插座中的多层引脚格栅阵列插入器，用于测试和转换具有非引脚栅格阵列封装的封装到引脚栅格阵列占位面积。 多层引脚格栅阵列插入器测试插座包括多层引脚格栅阵列插入器，安装在具有非栅格阵列封装的封装上的半导体器件和紧固件。 所述多层引脚格栅阵列插入件包括顶层信号层，其上表面具有接合焊盘，底部信号层在底表面上具有引脚格栅阵列占地面积，接地层之间的至少一个电源层， 顶部信号层和底部信号层，以及用于将多个接合焊盘连接到引脚栅极阵列覆盖区的引脚的链接。 紧固件将包装压靠在连接包装的引线与接合垫的多层销栅格阵列插入器上。

公开(公告)号：US06333563B1

公开(公告)日：2001-12-25

申请号：US09587944

申请日：2000-06-06

Applicant: Raymond A. Jackson ,  Anson J. Call ,  Mark G. Courtney ,  Stephen A. DeLaurentis ,  Mukta S. Farooq ,  Shaji Farooq ,  Lewis S. Goldmann ,  Gregory B. Martin ,  Sudipta K. Ray

Inventor： Raymond A. Jackson ,  Anson J. Call ,  Mark G. Courtney ,  Stephen A. DeLaurentis ,  Mukta S. Farooq ,  Shaji Farooq ,  Lewis S. Goldmann ,  Gregory B. Martin ,  Sudipta K. Ray

IPC: H01L2940

CPC classification number: H05K1/141 ,  H01L23/49833 ,  H01L2224/16 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/15311 ,  H05K3/284 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/10734 ,  H05K2201/10977

Abstract: The present invention relates generally to an electrical interconnection package and a method thereof. More particularly, the invention encompasses an invention that increases the fatigue life of a Ball Grid Array (BGA) electrical interconnection. This invention structurally couples at least one module to an organic interposer using a high modulus underfill material. The organic interposer is then joined to a organic board using standard joining processes. The inventive module can then be removed from the organic board at any time by moving the organic interposer using standard rework techniques.

Abstract translation: 本发明一般涉及电互连封装及其方法。 更具体地，本发明包括增加球栅阵列（BGA）电互连的疲劳寿命的发明。 本发明使用高模量底部填充材料将至少一个模块结构地耦合到有机插入件。 然后使用标准连接工艺将有机插入物连接到有机基板。 随后可以通过使用标准返工技术移动有机插入件，随时从有机板上移除本发明的模块。

公开(公告)号：US06313998B1

公开(公告)日：2001-11-06

申请号：US09285354

申请日：1999-04-02

Applicant: Kenneth J. Kledzik ,  Jason C. Engle

Inventor： Kenneth J. Kledzik ,  Jason C. Engle

IPC: H05K706

CPC classification number: H01L23/49861 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/141 ,  H05K3/3421 ,  H05K3/368 ,  H05K3/4092 ,  H05K7/1092 ,  H05K2201/049 ,  H05K2201/09754 ,  H05K2201/10515 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A circuit board assembly having integrated circuit packages vertically arranged three dimensionally is used to increase electronic component density without increasing the size of the circuit board. For a preferred embodiment of the circuit board assembly, the printed circuit board has at least one primary mounting pad array affixed thereto, each pad of the array having first and second portions. Each lead of a first integrated circuit package is conductively bonded to the first portion of a different mounting pad of said primary array. A package carrier having a plurality of carrier leads attached thereto and a secondary mounting pad array on an upper surface thereof, covers the first package. Each lead of the carrier is coupled to a different pad of the secondary array and is also conductively bonded to the second portion of a different mounting pad of the primary array. Each lead of a second integrated circuit package is conductively bonded to a different mounting pad of the secondary mounting pad array. For a preferred embodiment of the invention, the carrier is provided with embedded lead frame elements which form both the leads and the mounting pads of the carrier. The result is a circuit board assembly having lower component costs, lower assembly costs, and a lower profile than that of the first embodiment assembly.

Abstract translation: 使用具有三维垂直布置的集成电路封装的电路板组件来增加电子元件密度而不增加电路板的尺寸。 对于电路板组件的优选实施例，印刷电路板具有固定到其上的至少一个主安装焊盘阵列，阵列的每个焊盘具有第一和第二部分。 第一集成电路封装的每个引线导电地结合到所述主阵列的不同安装焊盘的第一部分。 具有附接到其上的多个载体引线和在其上表面上的辅助安装焊盘阵列的封装载体覆盖第一封装。 载体的每个引线耦合到次级阵列的不同焊盘，并且还导电地结合到主阵列的不同安装焊盘的第二部分。 第二集成电路封装的每个引线导电地接合到辅助安装焊盘阵列的不同安装焊盘。 对于本发明的优选实施例，载体设置有形成载体的引线和安装焊盘的嵌入式引线框架元件。 结果是具有比第一实施例组件更低的部件成本，更低的组装成本和更低的轮廓的电路板组件。

公开(公告)号：US20010024129A1

公开(公告)日：2001-09-27

申请号：US09843119

申请日：2001-04-26

Inventor： Salman Akram ,  Alan G. Wood ,  Warren M. Farnworth

IPC: G01R031/26

CPC classification number: H05K7/1061 ,  B33Y10/00 ,  B33Y30/00 ,  B33Y80/00 ,  G01R1/0408 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/07378 ,  G01R3/00 ,  H01L23/32 ,  H01L23/49827 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/8114 ,  H01L2224/81385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K1/112 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/049 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/167 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: An interposer including a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, with an interposer substrate. The fence may include edges that are configured to progressively align a semiconductor device with the interposer substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the interposer substrate. Methods for fabricating the fence include the use of stereolithographic and molding processes. When stereolithography is used to fabricate the fence, a machine vision system that includes at least one camera operably associated with a computer may be used to control a stereolithography apparatus and facilitates recognition of the position and orientation of interposer substrates on and around which material is to be applied in one or more layers to form the fence. As a result, the interposer substrates need not be precisely mechanically aligned.

Abstract translation: 一种插入器，其包括接纳半导体器件（例如倒装芯片型半导体器件）与栅介质基板的栅栏。 栅栏可以包括被配置为使半导体器件与插入器衬底逐渐对准的边缘。 挡板还可以包括一个或多个侧向凹入区域，以便于半导体器件与插入器基板的粗略对准。 围栏的制造方法包括使用立体光刻和成型工艺。 当使用立体光刻制造栅栏时，可以使用包括与计算机可操作地相关联的至少一个照相机的机器视觉系统来控制立体光刻设备并且有助于识别材料在其上和周围的插入物基板的位置和取向 应用于一层或多层以形成栅栏。 结果，内插器基板不需要精确地机械对准。

公开(公告)号：US06258623B1

公开(公告)日：2001-07-10

申请号：US09349522

申请日：1999-07-08

Applicant: Walter L. Moden ,  Jerrold L. King ,  Jerry M. Brooks

Inventor： Walter L. Moden ,  Jerrold L. King ,  Jerry M. Brooks

IPC: H01L2144

CPC classification number: H05K1/181 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/145 ,  H05K1/147 ,  H05K2201/049 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49169 ,  H01L2924/00

Abstract: A low profile multi-IC chip package for high speed application comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with busses formed on one side. In another embodiment, the connector comprises multiple busses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with busses within the cage, or, alternatively, are directly fixed to leads or pads on the host circuit board.

Abstract translation: 用于高速应用的低调多IC芯片封装包括用于电连接一组堆叠的初级半导体封装的等效外引线的连接器。 在一个实施例中，连接器包括两部分柔性绝缘聚合物片，其一面形成有总线。 在另一个实施例中，连接器包括由导电聚合物形成的多个母线。 在另外的实施例中，初级封装堆叠在保持架内并使其外部引线与保持架内的总线不连接接触，或者替代地，直接固定到主电路板上的引线或焊盘。

公开(公告)号：US20010006829A1

公开(公告)日：2001-07-05

申请号：US09792771

申请日：2001-02-23

Inventor： Walter L. Moden ,  Jerrold L. King ,  Jerry M. Brooks

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: H05K1/181 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/145 ,  H05K1/147 ,  H05K2201/049 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49169 ,  H01L2924/00

Abstract: A low profile multi-IC chip package for high speed application comprises a connector for electrically connecting the equivalent outer leads of a set of stacked primary semiconductor packages. In one embodiment, the connector comprises a two-part sheet of flexible insulative polymer with buses formed on one side. In another embodiment, the connector comprises multiple buses formed from conductive polymer. In further embodiments, the primary packages are stacked within a cage and have their outer leads in unattached contact with buses within the cage or, alternatively, are directly fixed to leads or pads on the host circuit board.

Abstract translation: 用于高速应用的低调多IC芯片封装包括用于电连接一组堆叠的初级半导体封装的等效外引线的连接器。 在一个实施例中，连接器包括两部分柔性绝缘聚合物片，其一端形成有总线。 在另一个实施例中，连接器包括由导电聚合物形成的多个总线。 在另外的实施例中，初级封装堆叠在保持架内并且使它们的外部引线与保持架内的总线不连接地接触，或者替代地直接固定到主电路板上的引线或焊盘上。

公开(公告)号：US06239485B1

公开(公告)日：2001-05-29

申请号：US09315785

申请日：1999-05-20

Applicant: Michael G. Peters ,  Wen-chou Vincent Wang ,  Yasuhito Takahashi ,  William Chou ,  Michael G. Lee ,  Solomon Beilin

Inventor： Michael G. Peters ,  Wen-chou Vincent Wang ,  Yasuhito Takahashi ,  William Chou ,  Michael G. Lee ,  Solomon Beilin

IPC: H01L2312

CPC classification number: H05K1/0219 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/141 ,  H05K1/144 ,  H05K3/20 ,  H05K2201/049 ,  H05K2201/055 ,  H05K2201/10378 ,  H01L2924/00

Abstract: An interposer for providing power, ground, and signal connections between an integrated circuit chip or chips and a substrate. The inventive interposer includes a signal core and external power/ground connection wrap. The two sections may be fabricated and tested separately, then joined together using z-connection technology. The signal core is formed from a conductive power/ground plane positioned between two dielectric layers. A patterned metal layer is formed on each dielectric layer. The two metal layers are interconnected by a through via or post process. The conductive power/ground plane functions to reduce signal cross-talk between signal lines formed on the two patterned metal layers. The power/ground wrap includes an upper substrate positioned above the signal core and a lower substrate positioned below the signal core. The upper and lower substrates of the power/ground wrap are formed from a dielectric film having a patterned metal layer on both sides, with the patterned layers connected by a through via or post process. The two power/ground wrap substrates may be formed separately or from one substrate which is bent into a desired form (e.g., a “U” shape). The two power/ground substrates are maintained in their proper alignment relative to the signal core and to each other by edge connectors which are also connected to the signal core's intermediary power/ground plane.

Abstract translation: 一种用于在集成电路芯片或芯片与基板之间提供电源，接地和信号连接的插入器。 本发明的插入器包括信号芯和外部电源/接地连接外壳。 这两个部分可以单独制造和测试，然后使用z连接技术连接在一起。 信号芯由位于两个电介质层之间的导电电源/接地平面形成。 在每个电介质层上形成图案化的金属层。 两个金属层通过通孔或后处理相互连接。 导电功率/接地面用于减少形成在两个图案化金属层上的信号线之间的信号串扰。 电源/接地包裹物包括位于信号芯上方的上基板和位于信号芯下方的下基板。 电源/接地线圈的上下基板由两面具有图案化金属层的电介质膜形成，图案化层通过通孔或后工艺连接。 两个电源/接地包覆基板可以分开地形成，或者可以从弯曲成所需形状（例如，“U”形状）的一个基板形成。 两个电源/接地基板相对于信号芯线保持正确的对准，并通过也连接到信号芯的中间电源/接地平面的边缘连接器彼此保持。

公开(公告)号：US06229218B1

公开(公告)日：2001-05-08

申请号：US09187477

申请日：1998-11-06

Applicant: William J. Casey ,  Andrew J. Heidelberg ,  Daniel C. Skinner

Inventor： William J. Casey ,  Andrew J. Heidelberg ,  Daniel C. Skinner

IPC: H01L2348

CPC classification number: H05K1/141 ,  H01L24/06 ,  H01L2224/05552 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01322 ,  H01L2924/15311 ,  H05K1/0295 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/09709 ,  H05K2201/099 ,  H05K2201/09954 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An interconnect device for connecting an electronic package, whether it be a single chip or a multi-component device, to a primary substrate requiring the mating of dissimilar solder patterns includes a secondary substrate having a first face and a second face. The first face of the secondary substrate may include a first pattern of conductive lands formed on the first face corresponding to a plurality of conductive leads of an electronic package. The second face of the secondary substrate includes a second pattern of conductive lands corresponding to a plurality of conductive lands formed on the primary substrate. The first pattern of conductive lands formed on the first face is electrically connected to the second pattern of conductive lands formed on the second face via surface and internal conductive paths. Solder ball reflow soldering methods are used to connect the electronic device to the secondary substrate and to connect the secondary substrate to the primary substrate.

Abstract translation: 用于将电子封装（无论是单芯片还是多组件器件）连接到需要不相似焊料图案的配合的主要衬底的互连装置包括具有第一面和第二面的次级衬底。 第二衬底的第一面可以包括形成在与电子封装的多个导电引线相对应的第一面上的导电焊盘的第一图案。 第二衬底的第二面包括对应于形成在主衬底上的多个导电焊盘的导电焊盘的第二图案。 形成在第一面上的导电焊盘的第一图案通过表面和内部导电路径电连接到形成在第二面上的导电焊盘的第二图案。 焊球回流焊接方法用于将电子器件连接到次级衬底并将次级衬底连接到初级衬底。