公开(公告)号：US07257792B2

公开(公告)日：2007-08-14

申请号：US10151368

申请日：2002-05-20

Applicant: Takeshi Nakayama ,  Hiroshi Ikeda ,  Shinichi Tanimoto

Inventor： Takeshi Nakayama ,  Hiroshi Ikeda ,  Shinichi Tanimoto

IPC: G06F17/50

CPC classification number: H05K3/0005 ,  G06F17/5072 ,  H05K1/0269 ,  H05K3/303 ,  H05K3/4644 ,  H05K2201/09227

Abstract: In a design aiding apparatus of the present invention, a plane clearance setting unit acquires information showing a predetermined margin, a component placement unit determines a placement area of a component such that, as seen in a lamination direction of a multilayer wiring board, at least one of the component and a pad connected to the component is included within a candidate area of a plane foil excluding a perimeter area, and a wiring unit determines a placement area of a wiring foil and a via in the same way that the placement area of the component is determined. Furthermore, in regard to a component, a component pad, a wiring foil, and a via whose placement areas have already been determined, a component placement inspection unit reports a design condition violation if the placement area of at least one of the component and the pad deviates outside the candidate area as seen in the lamination direction of the board, and a wiring inspection unit reports a design condition violation if the placement area of the wiring foil or the via deviates outside the candidate area as seen in the lamination direction of the board.

Abstract translation: 在本发明的设计辅助装置中，平面间隙设定单元获取表示预定余量的信息，部件放置单元确定部件的放置面积，使得从多层布线基板的层叠方向看，至少 连接到部件的部件和焊盘中的一个包括在除了周边区域之外的平面箔的候选区域内，并且布线单元以与布置箔和通孔的放置面积相同的方式确定布线箔和通孔的放置面积 确定组件。 此外，对于已经确定了放置区域的部件，部件焊盘，布线箔和通孔，如果部件和部件的至少一个的放置区域，则部件放置检查单元报告设计条件违反 如从电路板的层压方向看，偏移在候选区域外面，如果布线箔或通孔的放置区域偏离候选区域，则布线检查单元报告设计条件违反， 板。

公开(公告)号：US07199478B2

公开(公告)日：2007-04-03

申请号：US10156016

申请日：2002-05-29

Applicant: Sung-ho Jung

Inventor： Sung-ho Jung

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K7/10 ,  H05K7/12

CPC classification number: H05K3/3436 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/111 ,  H05K2201/09227 ,  H05K2201/094 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/10734 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A printed circuit board (PCB) having a plurality of lands corresponding to a plurality of solder pins provided on a semiconductor chip package, the lands provided adjacent to the border of the printed circuit board having a rectangular shape elongated in a direction toward the border, thus providing a printed circuit board which can achieve a simple design, improve the integration of peripheral chips mounted thereon, and secure a fine soldering state.

Abstract translation: 一种印刷电路板（PCB），具有与设置在半导体芯片封装上的多个焊接针相对应的多个焊盘，所述焊盘设置成邻近印刷电路板的边界，该矩形形状沿朝向边界的方向延伸， 从而提供可以实现简单设计的印刷电路板，改善安装在其上的外围芯片的集成，并确保精细的焊接状态。

公开(公告)号：US20070072342A1

公开(公告)日：2007-03-29

申请号：US11523153

申请日：2006-09-18

Applicant: William Cornelius ,  Paul Baker

Inventor： William Cornelius ,  Paul Baker

IPC: H01L21/00

CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6616 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15173 ,  H05K1/0231 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T29/49222 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The present invention provides an apparatus and methods for the functionality of an integrated circuit. An exemplary embodiment according to an aspect of the present invention includes a ball grid array having open spaces therein. Within the open spaces, pairs of opposite polarity vias are clustered to minimize current path inductance by exploiting mutual inductance between vias of opposite current flow. In an illustrative embodiment, capacitors are coupled to the vias to further reduce current path inductance.

公开(公告)号：US20070034405A1

公开(公告)日：2007-02-15

申请号：US11200041

申请日：2005-08-10

Applicant: Paul Brown

Inventor： Paul Brown

IPC: H05K1/11

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A printed circuit board having micro-vias used to connect a portion of the contacts in a selected row or column to the first internal layer of the board, thereby creating routing channels on the second and subsequent internal layers of the board between selected rows or columns of through-board vias used to connect the remaining contacts and a BGA package adapted to be used with the printed circuit board.

Abstract translation: 一种具有微通孔的印刷电路板，用于将所选行或列中的触点的一部分连接到电路板的第一内层，从而在所选行或列之间的板的第二和随后的内层上创建路由通道 用于连接剩余触点的通孔通孔和适合与印刷电路板一起使用的BGA封装。

公开(公告)号：US07161812B1

公开(公告)日：2007-01-09

申请号：US10442355

申请日：2003-05-20

Applicant: Simon A. Thomas

Inventor： Simon A. Thomas

IPC: H05K7/02

CPC classification number: H05K7/1084 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/10734

Abstract: A surface mount grid array implemented on a PCB (printed circuit board) optimized for trace escape routing for the PCB. The surface mount grid array includes a plurality of connection blocks, with each connection block including an array of pins and an array of vias, wherein the pins and vias are configured to communicatively connect an integrated circuit device to a plurality of traces of the PCB. The connection blocks are disposed in a tiled arrangement, wherein the connection blocks implement a plurality of trace escape channels along connection block boundaries. The trace escape channels are configured for routing traces from inner pins of the surface mount grid array to a periphery of the surface mount grid array.

Abstract translation: 在PCB（印刷电路板）上实现的表面安装栅格阵列，优化用于PCB的走线路由。 表面安装栅极阵列包括多个连接块，每个连接块包括一个引脚阵列和一个通孔阵列，其中引脚和通孔被配置为将集成电路器件通信连接到PCB的多个迹线。 连接块以平铺布置布置，其中连接块沿着连接块边界实现多个跟踪转义通道。 轨迹逃逸通道被配置为将表面安装网格阵列的内部引脚的轨迹路由到表面安装网格阵列的外围。

公开(公告)号：US20060255460A1

公开(公告)日：2006-11-16

申请号：US11127160

申请日：2005-05-12

Applicant: Irving Memis

Inventor： Irving Memis

IPC: H01L23/48

CPC classification number: H05K1/181 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0248 ,  H05K2201/0784 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/0401

Abstract: An electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of conductive lines which, to substantially prevent skew, are of substantially the same length. A method of making the package is also provided, as is a circuitized substrate and an information handling system, the latter adapted for having one or more of the electronic packages as part thereof.

Abstract translation: 一种电子封装，其包括具有定位在其上的至少两个电气部件的电路化基板。 该包装包括接触部位的图案，每个接触部位具有与其耦合的部件之一。 接触部位的图案依次通过一组导线相互电连接，导线基本上防止偏斜具有基本上相同的长度。 还提供了制造包装的方法，电路化基板和信息处理系统也是如此，后者适于将一个或多个电子包装作为其一部分。

公开(公告)号：US07112880B2

公开(公告)日：2006-09-26

申请号：US10991622

申请日：2004-11-17

Applicant: Bill Cornelius ,  Paul Baker

Inventor： Bill Cornelius ,  Paul Baker

IPC: H01L23/52 ,  H01L23/12 ,  H01L23/48

CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6616 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15173 ,  H05K1/0231 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T29/49222 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The present invention provides an apparatus and methods for the functionality of an integrated circuit. An exemplary embodiment according to an aspect of the present invention includes a ball grid array having open spaces therein. Within the open spaces, pairs of opposite polarity vias are clustered to minimize current path inductance by exploiting mutual inductance between vias of opposite current flow. In an illustrative embodiment, capacitors are coupled to the vias to further reduce current path inductance.

公开(公告)号：US20060164586A1

公开(公告)日：2006-07-27

申请号：US11337470

申请日：2006-01-24

Applicant: Kazuyuki Yamada

Inventor： Kazuyuki Yamada

IPC: G02F1/1345

CPC classification number: G02F1/13452 ,  G02F2001/13456 ,  H05K1/113 ,  H05K1/189 ,  H05K2201/0394 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/10674

Abstract: An electro-optical device includes an electro-optical panel, a flexible base member connected to the electro-optical panel, and an electronic component mounted on the flexible base member. Here, the electronic component has conductive terminals electrically connected to a plurality of terminals disposed on the flexible base member, the plurality of terminals are disposed on one surface of the flexible base member, and the conductive terminals and the plurality of terminals two-dimensionally overlap with each other. The flexible base member has first wires which are connected to the plurality of terminals and disposed on the one surface thereof, hole portions formed in the flexible base member to correspond to at least one terminal of the plurality of terminals, and second wires which are connected to the at least one terminals through connection members disposed in the hole portions and are disposed on the other surface of the flexible base member opposite to the one surface. The hole portions two-dimensionally overlap with the conductive terminals and the plurality of terminals.

Abstract translation: 电光装置包括电光面板，连接到电光面板的柔性基底构件和安装在柔性基底构件上的电子部件。 这里，电子部件具有与设置在柔性基体上的多个端子电连接的导电端子，多个端子配置在柔性基体的一个面上，导电端子和多个端子二维重叠 与彼此。 柔性基体具有连接到多个端子并且设置在其一个表面上的第一导线，形成在柔性基底构件中的孔部分对应于多个端子中的至少一个端子，以及连接的第二导线 通过设置在孔部中的连接构件连接到至少一个端子，并且设置在与一个表面相对的柔性基底构件的另一个表面上。 孔部与导电端子和多个端子二维地重叠。

公开(公告)号：US20060154402A1

公开(公告)日：2006-07-13

申请号：US11277042

申请日：2006-03-21

Applicant: Chung-Yi Fang ,  Tze-Hsiang Chao ,  Yi-Show Su

Inventor： Chung-Yi Fang ,  Tze-Hsiang Chao ,  Yi-Show Su

IPC: H01L21/50

CPC classification number: H05K1/112 ,  G06F17/5077 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/15173 ,  H05K1/0219 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/10674 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A method for routing a plurality of signal traces out of a plurality of corresponding bumper pads for implementation of a die on a multi-layer circuit board includes utilizing the plurality of bumper pads positioned in a periphery area of the die; utilizing a plurality of power/ground bumper pads positioned in a center area of the die; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of first-layer traces being routed in a first layer of the multi-layer circuit board; assigning a plurality of signal traces corresponding to a plurality of bumper pads as a plurality of second-layer traces being routed in a second layer of the multi-layer circuit board; routing the plurality of first-layer traces straight away from the die; and routing the plurality of second-layer traces with a turn not to be vertically underneath the first-layer traces.

Abstract translation: 一种用于从多个对应的缓冲垫中路由多个信号迹线的方法，用于在多层电路板上实现管芯包括利用位于管芯的周边区域中的多个保险杠垫; 利用位于模具的中心区域中的多个电源/接地保险杠垫; 在多层电路板的第一层中路由多个第一层迹线，分配对应于多个保险杠垫的多个信号迹线; 在多层电路板的第二层中路由多个第二层迹线，分配对应于多个保险杠焊盘的多个信号迹线; 将多个第一层迹线直接远离模具布置; 以及以不垂直于第一层迹线下方的转弯来路由多个第二层迹线。

公开(公告)号：US07069646B2

公开(公告)日：2006-07-04

申请号：US10407460

申请日：2003-04-07

Applicant: Guy M. A. F. Duxbury ,  Aneta Wyrzykowska ,  Luigi G. Difilippo ,  Herman Kwong

Inventor： Guy M. A. F. Duxbury ,  Aneta Wyrzykowska ,  Luigi G. Difilippo ,  Herman Kwong

IPC: H05K3/36

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734 ,  Y10T29/49016 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Techniques for reducing the number of layers in a multilayer signal routing device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method wherein the multilayer signal routing device has a plurality of electrically conductive signal path layers for routing a plurality of electrical signals thereon. The method may comprise forming a plurality of electrically conductive vias in the multilayer signal routing device for electrically connecting at least two of the plurality of electrically conductive signal path layers, wherein the plurality of vias are arranged so as to form at least one channel in at least one other of the plurality of electrically conductive signal path layers. The method may also comprise grouping at least a portion of the plurality of electrical signals based at least in part upon their proximity to the at least one channel so that they may be efficiently routed therein.

Abstract translation: 公开了用于减少多层信号路由设备中的层数的技术。 在一个特定的示例性实施例中，这些技术可以被实现为一种方法，其中多层信号路由设备具有用于在其上路由多个电信号的多个导电信号路径层。 所述方法可以包括在所述多层信号路由设备中形成多个导电通孔，用于电连接所述多个导电信号路径层中的至少两个，其中所述多个通孔被布置成在其中形成至少一个通道 多个导电信号路径层中的至少另一个。 该方法还可以包括至少部分地基于它们与至少一个信道的接近度来分组多个电信号的至少一部分，使得它们可以被有效地路由到其中。