公开(公告)号：US20070108619A1

公开(公告)日：2007-05-17

申请号：US11274016

申请日：2005-11-15

Applicant: Jun Hsu

Inventor： Jun Hsu

IPC: H01L29/40

CPC classification number: H05K1/112 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H05K1/116 ,  H05K3/244 ,  H05K3/421 ,  H05K2201/09436 ,  H05K2201/09463 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09663 ,  H01L2924/00

Abstract: A bonding pad with high bonding strength to a solder ball and a bump includes a carrier, a wiring layer formed on the carrier, a protection layer formed on top of the wiring layer and a solder mask layer surrounded around the protection layer and the wiring layer to form a bonding pad opening. The protection layer is extended outside the bonding pad opening such that when solder are extended into the bonding pad opening, the solder balls engage with side faces defining the bump pad opening as well as the protection layer outside the bump pad opening and a bonding strength between the bonding pad and the solder performance is increased.

Abstract translation: 具有对焊球和凸块具有高结合强度的接合焊盘包括载体，形成在载体上的布线层，形成在布线层顶部的保护层和围绕保护层和布线层围绕的焊料掩模层 以形成接合焊盘开口。 保护层延伸到接合焊盘开口的外部，使得当焊料延伸到焊盘开口中时，焊球与限定凸块焊盘开口的侧面以及凸块焊盘开口之外的保护层接合， 焊盘和焊料性能提高。

公开(公告)号：US07183647B2

公开(公告)日：2007-02-27

申请号：US10709096

申请日：2004-04-13

Applicant: Kei Murayama ,  Masahiro Sunohara

Inventor： Kei Murayama ,  Masahiro Sunohara

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/562 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/81206 ,  H01L2224/81801 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H05K1/113 ,  H05K3/328 ,  H05K2201/09436 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10674 ,  H05K2203/0285 ,  H01L2924/00

Abstract: In a wiring substrate of the present invention in which a bump of an electronic parts is bonded to a connection pad of a wiring pattern provided on an insulating film by an ultrasonic flip-chip packaging, a via hole into which a via post acting as a strut to support the connection pad upon the ultrasonic flip-chip packaging is filled is arranged in the insulating film under the connection pad.

Abstract translation: 在本发明的布线基板中，电子部件的凸块通过超声波倒装芯片封装被接合到设置在绝缘膜上的布线图案的连接焊盘，通孔，通孔作为 在超声波倒装芯片封装被填充的支撑件支撑连接垫被布置在连接垫下面的绝缘膜中。

公开(公告)号：US20070000685A1

公开(公告)日：2007-01-04

申请号：US10572556

申请日：2004-09-28

Applicant: Shuichi Inoue

Inventor： Shuichi Inoue

IPC: H05K1/03

CPC classification number: H05K1/117 ,  H01R12/523 ,  H01R13/2414 ,  H05K1/0237 ,  H05K3/403 ,  H05K3/4611 ,  H05K2201/0133 ,  H05K2201/0919 ,  H05K2201/09436

Abstract: A first high speed transmission line board (1) having a stripline structure is composed of a first elastomer sheet (1A) that has a fixed dielectric constant, plural first elastomer strips (1B) that are conductive, arrayed at two edges of the first elastomer sheet (1A), and plural first high speed transmission lines (1C) formed in a pattern connecting two ends of the first elastomer strips (1B). A first surface layer board (2) is composed of a second elastomer sheet (2A) that is nonconductive, and plural second elastomer strips (2B) that are conductive, arrayed similarly to the first elastomer strips (1B), at two edges of the second elastomer sheet (2A). A multilayer board is configured by laminating the first surface layer board (2) on the first high speed transmission line board (1), and external connecting terminals are in pressurized contact with the plural second elastomer strips (2B), so that the plural first high speed transmission lines (1C) are connected.

Abstract translation: 具有带状线结构的第一高速传输线路板（1）由具有固定介电常数的第一弹性体片（1A）和导电的多个第一弹性体带（1B）组成，排列在 第一弹性体片（1A）和形成为连接第一弹性体带（1B）的两端的图案的多个第一高速传输线（1C）。 第一表面层板（2）由不导电的第二弹性体片（2A）和与第一弹性体带（1B）类似地排列成导电的多个第二弹性体带（2B）组成，两个 第二弹性体片（2A）的边缘。 通过在第一高速传输线路板（1）上层压第一表面层板（2）并且外部连接端子与多个第二弹性体带（2B）加压接触而构成多层板，使得多个 第一高速传输线（1C）连接。

公开(公告)号：US07157362B2

公开(公告)日：2007-01-02

申请号：US11020618

申请日：2004-12-21

Applicant: Hiroyuki Yatsu ,  Nobuyuki Suzuki

Inventor： Hiroyuki Yatsu ,  Nobuyuki Suzuki

IPC: H01L21/44

CPC classification number: H01L25/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/181 ,  H05K2201/09436 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/1572 ,  Y02P70/611 ,  H01L2224/05599

Abstract: An electronic circuit unit contains electrodes to which bumps of a semiconductor chip are adhered. The electrodes are arranged on an upper surface of a circuit board. Land units to which chip parts is soldered are arranged on a rear surface of the circuit board. such that an insulating plate which is on the rear surface of the circuit board is supported by a supporting jig during a mounting process of the semiconductor chip, and the circuit board is not tilted. Therefore, an electronic circuit unit ensuring that the semiconductor chip is mounted with a reliable mounting capability can be obtained.

Abstract translation: 电子电路单元包含附着有半导体芯片的凸点的电极。 电极布置在电路板的上表面上。 在电路板的后表面上布置有焊接有芯片部件的接地单元。 使得在半导体芯片的安装处理期间，在电路板的后表面上的绝缘板由支撑夹具支撑，并且电路板不倾斜。 因此，可以获得确保半导体芯片安装有可靠的安装能力的电子电路单元。

公开(公告)号：US20060279000A1

公开(公告)日：2006-12-14

申请号：US11407185

申请日：2006-04-20

Applicant: Ruei-Chih Chang ,  Chu-Chin Hu

Inventor： Ruei-Chih Chang ,  Chu-Chin Hu

IPC: H01L21/44 ,  H01L21/4763 ,  H01L23/48

CPC classification number: H05K3/4007 ,  H01L23/49816 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1147 ,  H01L2224/13109 ,  H01L2224/13609 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/14 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2203/043 ,  H05K2203/054 ,  H05K2203/0723 ,  H01L2224/29099 ,  H01L2224/05599

Abstract: A pre-solder structure on a semiconductor package substrate and a method for fabricating the same are proposed. A plurality of conductive pads are formed on the substrate, and a protective layer having a plurality of openings for exposing the conductive pads is formed over the substrate. A conductive seed layer is deposited over the protective layer and openings. A patterned resist layer is formed on the seed layer and has openings corresponding in position to the conductive pads. A plurality of conductive pillars and a solder material are deposited in sequence in each of the openings. The resist layer and the seed layer not covered by the conductive pillars and the solder material are removed. The solder material is subject to a reflow-soldering process to form pre-solder bumps covering the conductive pillars.

Abstract translation: 提出了半导体封装基板上的预焊结构及其制造方法。 在衬底上形成多个导电焊盘，并且在衬底上形成具有用于暴露导电焊盘的多个开口的保护层。 导电种子层沉积在保护层和开口上。 在种子层上形成图案化的抗蚀剂层，并且具有与导电焊盘相对应的位置的开口。 在每个开口中依次沉积多个导电柱和焊料。 除去未被导电柱和焊料材料覆盖的抗蚀剂层和籽晶层。 焊料材料经受回流焊接工艺以形成覆盖导电柱的预焊凸块。

公开(公告)号：US20060225917A1

公开(公告)日：2006-10-12

申请号：US11360099

申请日：2006-02-22

Applicant: Wen-Hung Hu

Inventor： Wen-Hung Hu

IPC: H05K1/09 ,  H05K3/12

CPC classification number: H05K1/113 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/09436 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/054 ,  Y10T29/49147

Abstract: A conductive bump structure of a circuit board and a fabrication method thereof are proposed. The circuit board is formed with conductive circuits on a surface thereof An insulating protection layer having a plurality of openings to expose terminals of the conductive circuits is formed on the circuit board. A conductive layer is formed on the insulating protection layer and in the openings thereof. A patterned resist layer is formed on the conductive layer and has a plurality of openings corresponding in position to the terminals of the conductive circuits. Conductive bumps are formed by electroplating in the openings of the resist layer. Then, the resist layer and the conductive layer underneath the resist layer are removed. An adhesive layer is formed on the conductive bumps and completely covers exposed surfaces of the conductive bumps respectively. The circuit board can be electrically connected to electronic elements through the conductive bumps.

Abstract translation: 提出了电路板的导电凸块结构及其制造方法。 电路板在其表面上形成有导电电路。在电路板上形成具有多个开口以露出导电电路端子的绝缘保护层。 在绝缘保护层及其开口中形成导电层。 图案化的抗蚀剂层形成在导电层上，并具有与导电电路的端子对应的多个开口。 导电凸块通过电镀在抗蚀剂层的开口中形成。 然后，去除抗蚀剂层和抗蚀剂层下面的导电层。 在导电凸块上形成粘合剂层，并分别完全覆盖导电凸块的暴露表面。 电路板可以通过导电凸块电连接到电子元件。

公开(公告)号：US07077927B2

公开(公告)日：2006-07-18

申请号：US10748548

申请日：2003-12-30

Applicant: Frank J. Bottari ,  Andrea C. Marble

Inventor： Frank J. Bottari ,  Andrea C. Marble

IPC: B29C65/02 ,  B32B37/02 ,  B32B37/14 ,  B32B37/20 ,  B32B38/14

CPC classification number: G06F3/045 ,  G06F2203/04113 ,  H05K3/20 ,  H05K3/207 ,  H05K3/28 ,  H05K2201/0284 ,  H05K2201/09436 ,  H05K2203/0531 ,  Y10T428/24917

Abstract: A method of applying an edge electrode pattern to a touch screen. The method includes depositing, on a first surface of a decal strip, conductive material in the form of an edge electrode pattern, placing the first surface of the decal strip on one edge of a touch screen, applying heat and pressure to an opposite surface of the decal strip until the edge electrode pattern is transferred from the first surface of the decal strip to the touch screen; and removing the decal strip.

公开(公告)号：US20060096778A1

公开(公告)日：2006-05-11

申请号：US11261393

申请日：2005-10-27

Applicant: Chang Yun

Inventor： Chang Yun

IPC: H05K1/11

CPC classification number: H01M10/48 ,  H01M10/425 ,  H05K1/0259 ,  H05K1/0298 ,  H05K1/113 ,  H05K2201/09436 ,  H05K2201/09781

Abstract: A protective circuit board for a battery pack for controlling charge and discharge states of the battery pack includes an insulation layer and a first signal pattern disposed inside the insulation layer. The circuit can further include a second signal pattern disposed inside the insulation layer. The circuit can include a first dummy pattern spaced from a first side of the first signal pattern and a second dummy pattern spaced from a second side of the first signal pattern.

Abstract translation: 一种用于控制电池组的充电和放电状态的电池组的保护电路板包括绝缘层和设置在绝缘层内部的第一信号图案。 电路还可以包括设置在绝缘层内部的第二信号图案。 电路可以包括与第一信号图案的第一侧间隔开的第一伪图案和与第一信号图案的第二侧间隔开的第二虚设图案。

公开(公告)号：US20060017873A1

公开(公告)日：2006-01-26

申请号：US11208781

申请日：2005-08-23

Applicant: Dong-Gyu Kim

Inventor： Dong-Gyu Kim

IPC: G02F1/1337

CPC classification number: G02F1/13458 ,  G02F1/13452 ,  G02F2001/133357 ,  G02F2001/133388 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/114 ,  H05K1/117 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/09436 ,  H01L2224/0401

Abstract: Disclosed are a liquid crystal display (LCD) and a method for manufacturing the same, in which connection stability is improved when connecting a COG, a COF, or an FPC to a driving circuit. A substrate of the LCD has a display region and a non-display region at a peripheral area thereof. Terminals are provided to electrically connect an external circuit and a circuit of the display region to ends of signal lines extended from the display region and the non-display region. A flat protective layer is formed on the terminals. A plurality of pads are respectively formed of a first contact region and a flat second contact region, and each of the pads contacts a corresponding terminal, which is formed through a pad contact hole formed on the protective layer, at the first contact region, and each of the pads is electrically connected through an anisotropic conductive resin to a terminal of the external circuit by a pressing process at the flat second contact region.

公开(公告)号：US20050189650A1

公开(公告)日：2005-09-01

申请号：US11120234

申请日：2005-05-02

Applicant: Jin Lee ,  Ming Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

Inventor： Jin Lee ,  Ming Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC: H01L21/44 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/485 ,  H01L23/525 ,  H04B1/707 ,  H04B7/26 ,  H05K3/10 ,  H05K3/24 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/12 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0949 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.