公开(公告)号：US20090225525A1

公开(公告)日：2009-09-10

申请号：US12466940

申请日：2009-05-15

Applicant: Yasuhiko Mano ,  Takashi Kariya ,  Shinobu Kato

Inventor： Yasuhiko Mano ,  Takashi Kariya ,  Shinobu Kato

IPC: H05K7/00

CPC classification number: H05K3/4046 ,  H01F17/0006 ,  H01F17/06 ,  H01F41/046 ,  H01F2017/002 ,  H01F2017/065 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0233 ,  H05K1/115 ,  H05K1/185 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/086 ,  H05K2201/09581 ,  Y10T29/4902 ,  H01L2224/05599

Abstract: An inductor embedded in a printed wiring board includes a conductor extending in the thickness direction of a printed circuit board and a magnetic body that is in contact with the conductor with no gap therebetween. For example, the magnetic body is composed of ferrite having a cylindrical tubular shape. The conductor is composed of a copper film formed by plating on an inner peripheral surface of the cylindrical tubular ferrite. The inductor is inserted in the thickness direction of the printed wiring board.

公开(公告)号：US20090095509A1

公开(公告)日：2009-04-16

申请号：US12188736

申请日：2008-08-08

Applicant: Shin Hirano ,  Kenji Iida ,  Yasutomo Maehara ,  Tomoyuki Abe ,  Takashi Nakagawa ,  Hideaki Yoshimura ,  Seigo Yamawaki ,  Norikazu Ozaki

Inventor： Shin Hirano ,  Kenji Iida ,  Yasutomo Maehara ,  Tomoyuki Abe ,  Takashi Nakagawa ,  Hideaki Yoshimura ,  Seigo Yamawaki ,  Norikazu Ozaki

IPC: H05K1/00 ,  H05K3/10

CPC classification number: H05K9/00 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4691 ,  H05K2201/0281 ,  H05K2201/0323 ,  H05K2201/09581 ,  H05K2201/0959 ,  H05K2201/09809 ,  Y10T29/49155

Abstract: In the core substrate, short circuit between an electrically conductive core section and a plated through-hole section can be securely prevented and cables can be formed in a high dense state. The core substrate comprises: the electrically conductive core section having a pilot hole, through which the plated through-hole section is formed; cable layers being respectively laminated on the both side faces of the core section; a plated layer coating an inner face of the pilot hole; and an insulating material filling a space between the plated layer and an outer circumferential face of the plated through-hole section.

Abstract translation: 在芯基板中，可以可靠地防止导电芯部与电镀通孔部之间的短路，并且可以以高致密状态形成电缆。 芯基板包括：导电芯部分具有导孔，电镀通孔部分穿过该引导孔; 电缆层分别层叠在芯部的两个侧面上; 涂覆导向孔的内表面的镀层; 以及填充所述镀层与所述电镀通孔部的外周面之间的空间的绝缘材料。

公开(公告)号：US20070257761A1

公开(公告)日：2007-11-08

申请号：US11429157

申请日：2006-05-08

Applicant: Yasuhiko Mano ,  Takashi Kariya ,  Shinobu Kato

Inventor： Yasuhiko Mano ,  Takashi Kariya ,  Shinobu Kato

IPC: H01F5/00

CPC classification number: H05K3/4046 ,  H01F17/0006 ,  H01F17/06 ,  H01F41/046 ,  H01F2017/002 ,  H01F2017/065 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0233 ,  H05K1/115 ,  H05K1/185 ,  H05K3/42 ,  H05K3/4602 ,  H05K2201/086 ,  H05K2201/09581 ,  Y10T29/4902 ,  H01L2224/05599

Abstract: An inductor embedded in a printed wiring board includes a conductor extending in the thickness direction of a printed circuit board and a magnetic body that is in contact with the conductor with no gap therebetween. For example, the magnetic body is composed of ferrite having a cylindrical tubular shape. The conductor is composed of a copper film formed by plating on an inner peripheral surface of the cylindrical tubular ferrite. The inductor is inserted in the thickness direction of the printed wiring board.

Abstract translation: 嵌入印刷电路板的电感器包括沿着印刷电路板的厚度方向延伸的导体和与导体接触而不间隙的磁体。 例如，磁性体由具有圆柱形管状的铁氧体构成。 导体由在圆筒形管状铁氧体的内周面上电镀形成的铜膜构成。 电感器沿印刷电路板的厚度方向插入。

公开(公告)号：US20070169959A1

公开(公告)日：2007-07-26

申请号：US11338402

申请日：2006-01-24

Applicant: Hanyi Ding ,  Brian Welch

Inventor： Hanyi Ding ,  Brian Welch

IPC: H05K1/16

CPC classification number: H05K1/024 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/0792 ,  H05K2201/09581 ,  H01L2924/00

Abstract: A microelectronic device and method of making the microelectronic device is provided. A dielectric substrate having first and second surfaces is provided. A first component, located in the dielectric substrate between the first and second surfaces of the dielectric substrate is formed. The first component includes a first interface and a second interface. A second component located in the dielectric substrate and spaced relative to the first component is formed, and a first low permittivity material is formed having a predetermined thickness and a first and second surface, the first surface of the low permittivity material is adjacent to or in contact with a first portion of the first interface of the first component. The first low permittivity material substantially reduces capacitive parasitics of the first component, resulting in a substantially higher characteristic impedance of the first component during operation of the microelectronic device.

Abstract translation: 提供微电子器件和制造微电子器件的方法。 提供具有第一和第二表面的电介质基片。 形成位于电介质基板之间的电介质基板的第一和第二表面之间的第一部件。 第一组件包括第一接口和第二接口。 形成位于电介质基板中并相对于第一部件间隔开的第二部件，并且形成具有预定厚度的第一低介电常数材料和第一和第二表面，低介电常数材料的第一表面邻近或位于 与第一部件的第一界面的第一部分接触。 第一低介电常数材料显着地减小了第一部件的电容寄生效应，导致在微电子器件工作期间第一部件的特征阻抗基本上更高。

公开(公告)号：US07168164B2

公开(公告)日：2007-01-30

申请号：US10234772

申请日：2002-09-04

Applicant: Rebecca A. Jessep ,  Terrance J. Dishongh ,  Carolyn R. McCormick ,  Thomas O. Morgan

Inventor： Rebecca A. Jessep ,  Terrance J. Dishongh ,  Carolyn R. McCormick ,  Thomas O. Morgan

IPC: H01K3/10

CPC classification number: H05K1/024 ,  G01B11/2441 ,  G01B11/255 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/445 ,  H05K2201/0187 ,  H05K2201/09309 ,  H05K2201/09581 ,  H05K2201/09718 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: Methods to shield conductive layer from via. A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.

Abstract translation: 屏蔽导电层通孔的方法。 在印刷电路板的导电层中的间隙孔周围形成绝缘材料的保护涂层，使得间隙孔内的通路中的导电材料不会接触导电层并产生短路。 在一个实施例中，保护涂层足够难以偏转用于钻通孔的钻头，从而防止不配准的钻孔。

公开(公告)号：US07091589B2

公开(公告)日：2006-08-15

申请号：US10497536

申请日：2003-12-10

Applicant: Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

Inventor： Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

IPC: H01L23/02

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/0366 ,  H05K1/162 ,  H05K3/0041 ,  H05K3/0044 ,  H05K3/388 ,  H05K3/4061 ,  H05K3/4069 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/09763 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/1338 ,  H05K2203/1581 ,  Y10T29/43 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

Abstract translation: 在层叠在所述芯板的一个表面上的芯板，布线层和电绝缘层的多层布线基板中，所述芯板的XY方向的热膨胀系数在2〜20ppm的范围内 所述芯板的核心部件是选自硅，陶瓷，玻璃，玻璃 - 环氧复合材料和金属的核心部件，所述芯板设置有多个在正面和背面之间导电的通孔 通过导电材料，并且在所述芯板的一个表面上设置电容器，其中所述电容器包括在所述通孔中作为导电材料的上电极和设置成经由电介质层面对所述上电极的下电极 。

公开(公告)号：US07062117B2

公开(公告)日：2006-06-13

申请号：US11215044

申请日：2005-08-31

Applicant: Mamoru Uchida

Inventor： Mamoru Uchida

IPC: G02B6/12

CPC classification number: H05K1/0274 ,  G02B6/43 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/115 ,  H05K2201/09581 ,  Y10T428/31612 ,  Y10T428/31678 ,  H01L2224/0401

Abstract: In a layered board, an insulating layer is interposed between a first layer capable of transmitting an electrical signal or an optical signal and a second layer capable of transmitting the electrical signal or the optical signal, interconnection of the signal between the first layer and the second layer is established through a signal connecting path penetrating the insulating layer, and the signal connecting path has both a function of transmitting the electrical signal and a function of transmitting the optical signal.

公开(公告)号：US07059044B2

公开(公告)日：2006-06-13

申请号：US10380661

申请日：2002-07-17

Applicant: Toshihiro Nishii

Inventor： Toshihiro Nishii

IPC: B32B15/08 ,  B05D3/02

CPC classification number: H05K3/4626 ,  H05K1/0366 ,  H05K1/0373 ,  H05K3/002 ,  H05K3/0032 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4632 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/029 ,  H05K2201/0355 ,  H05K2201/09581 ,  H05K2203/0191 ,  H05K2203/065 ,  H05K2203/083 ,  H05K2203/1461 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49135 ,  Y10T29/49146 ,  Y10T428/24917

Abstract: For the purpose of achieving enhanced reliability with respect to interlayer connections of printed wiring boards, a manufacturing method of printed wiring boards of the present invention includes any one of the steps of A) restricting the resin flowing in hot press processing, B) joining fiber reinforcements together by fusion or adhesion, C) having the thickness of a board material reduced after a filling process and D) forming a low fluidity layer via a filler mixed in a board material. Such properties as allowing the resin flowing in hot press processing to be controlled are provided to a material for manufacturing printed wiring boards of the present invention or to a volatile ingredient contained therein to allow the thickness of a board material to be reduced efficiently after a filling process.

Abstract translation: 为了实现印刷电路板的层间连接增强的可靠性，本发明的印刷电路板的制造方法包括以下步骤之一：A）限制在热压加工中流动的树脂，B）将纤维 通过熔融或粘合在一起的增强物，C）在填充过程之后具有减少的板材料的厚度，以及D）通过混合在板材料中的填料形成低流动性层。 本发明的印刷电路板制造用的材料或其中含有的挥发性成分的材料被提供给允许在热压加工中流动的树脂的特性，以便在填充后能够有效地降低板材的厚度 处理。

公开(公告)号：US20050281008A1

公开(公告)日：2005-12-22

申请号：US11202248

申请日：2005-08-12

Applicant: Jiangqi He ,  Ping Sun ,  Hyunjun Kim ,  Xiang Zeng

Inventor： Jiangqi He ,  Ping Sun ,  Hyunjun Kim ,  Xiang Zeng

IPC: H01G4/228 ,  H01L23/498 ,  H01L23/50 ,  H05K1/00 ,  H05K1/03 ,  H05K1/16

CPC classification number: H01G4/228 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19103 ,  H05K1/0306 ,  H05K1/162 ,  H05K2201/0187 ,  H05K2201/0394 ,  H05K2201/09581 ,  H05K2201/10378 ,  H05K2201/10674

Abstract: Extending high k material of a second dielectric layer to surround at least one thru-via designed to provide a signal other than a power signal to a die may eliminate discrete AC coupling capacitors to reduce cost and improve performance of the package.

Abstract translation: 扩展第二电介质层的高k材料以围绕设计成向芯片提供除了功率信号之外的信号的至少一个通孔可以消除离散的AC耦合电容器以降低成本并提高封装的性能。

公开(公告)号：US20050012217A1

公开(公告)日：2005-01-20

申请号：US10497536

申请日：2003-12-10

Applicant: Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

Inventor： Toshiaki Mori ,  Kazunori Nakamura ,  Satoru Kuramochi ,  Miyuki Akazawa ,  Koichi Nakayama

IPC: H01L23/498 ,  H05K1/03 ,  H05K1/16 ,  H05K3/00 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/0366 ,  H05K1/162 ,  H05K3/0041 ,  H05K3/0044 ,  H05K3/388 ,  H05K3/4061 ,  H05K3/4069 ,  H05K3/4076 ,  H05K3/426 ,  H05K3/4605 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/09763 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/1338 ,  H05K2203/1581 ,  Y10T29/43 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.

Abstract translation: 在层叠在所述芯板的一个表面上的芯板，布线层和电绝缘层的多层布线基板中，所述芯板的XY方向的热膨胀系数在2〜20ppm的范围内 所述芯板的核心部件是选自硅，陶瓷，玻璃，玻璃 - 环氧复合材料和金属的核心部件，所述芯板设置有多个在正面和背面之间导电的通孔 通过导电材料，并且在所述芯板的一个表面上设置电容器，其中所述电容器包括在所述通孔中作为导电材料的上电极和设置成经由电介质层面对所述上电极的下电极 。