Surface mount technology to via-in-pad interconnections
    112.
    发明授权
    Surface mount technology to via-in-pad interconnections 有权
    表面贴装技术可以通过板内互连

    公开(公告)号:US06927346B2

    公开(公告)日:2005-08-09

    申请号:US10326901

    申请日:2002-12-20

    Abstract: Apparatus and methods for interconnecting a SMT component interconnect to a via-in-pad (VIP) interconnect. A first reflowable material is deposited on the VIP bond pad. A sphere having a higher melt temperature than the reflow temperature of the first interconnect material is deposited on the first interconnect material. A first reflow process is performed to interconnect the sphere and the VIP bond pad while the sphere remains solid, and the first reflowable material preventing the first interconnect material from migrating into the via-in-pad.

    Abstract translation: 用于将SMT组件互连件互连到通孔式(VIP)互连的装置和方法。 第一个可回流材料沉积在VIP接合垫上。 具有比第一互连材料的回流温度更高的熔融温度的球体沉积在第一互连材料上。 执行第一回流工艺以在球体保持固体的同时使球体和VIP接合焊盘互连,并且第一可回流材料防止第一互连材料迁移到通孔内焊盘。

    Apparatus and method for force mounting semiconductor packages to printed circuit boards
    116.
    发明授权
    Apparatus and method for force mounting semiconductor packages to printed circuit boards 有权
    将半导体封装强制安装到印刷电路板的装置和方法

    公开(公告)号:US06823582B1

    公开(公告)日:2004-11-30

    申请号:US10211440

    申请日:2002-08-02

    Abstract: An apparatus and method for force mounting semiconductor packages onto printed circuit boards without the use of solder. The apparatus includes a substrate, a first integrated circuit die mounted onto the substrate, a housing configured to house the first integrated circuit die mounted onto the substrate, and a force mechanism configured to force mount the housing including the integrated circuit die and substrate onto a printed circuit board. The method includes mounting a first integrated circuit die onto a first surface of a substrate, housing the first integrated circuit die mounted onto the substrate in a housing, and using a force mechanism to force mount the housing including the first integrated circuit die mounted on the substrate onto a printed circuit board. According to various embodiments, the force mechanism includes one of the following types of force mechanisms clamps, screws, bolts, adhesives, epoxy, or Instrument housings or heat stakes.

    Abstract translation: 一种在不使用焊料的情况下将半导体封装强制安装到印刷电路板上的装置和方法。 该装置包括基板,安装在基板上的第一集成电路芯片,被构造成容纳安装在基板上的第一集成电路芯片的壳体,以及强制机构,其被构造成将包括集成电路管芯和基板的壳体安装到 印刷电路板。 该方法包括将第一集成电路管芯安装到衬底的第一表面上,将安装在衬底上的第一集成电路管芯容纳在壳体中,并且使用力机构来强制安装壳体,该壳体包括安装在衬底上的第一集成电路管芯 衬底到印刷电路板上。 根据各种实施例,力机构包括以下类型的力机构夹具,螺钉,螺栓,粘合剂,环氧树脂或仪器壳体或热桩中的一种。

    Piezoelectric oscillator and its manufacturing method
    118.
    发明申请
    Piezoelectric oscillator and its manufacturing method 有权
    压电振荡器及其制造方法

    公开(公告)号:US20040113708A1

    公开(公告)日:2004-06-17

    申请号:US10475072

    申请日:2003-10-17

    Abstract: A piezoelectric oscillator comprising a piezoelectric vibrator with a piezoelectric vibrating element housed in a package and bottom terminals formed on the outer side of the bottom of the package, a circuit board with at least one electronic circuit component mounted and conductor patterns formed on the top side, and columnlike supports which mechanically and electrically connects the bottom terminals of the piezoelectric vibrator and the conductor patterns on the circuit board. The piezoelectric oscillator has a smaller board occupation area, and can be manufactured by quantity production using a batch process at a high productivity and a reduced cost.

    Abstract translation: 一种压电振荡器,包括压电振动器,其具有容纳在封装中的压电振动元件和形成在所述封装的底部的外侧上的底端子;电路板,具有安装的至少一个电子电路部件和形成在所述顶侧上的导体图案 和柱状支撑体,其将压电振动器的底端和电路板上的导体图案机械地和电连接。 压电振荡器具有较小的板占用面积,并且可以通过以高生产率和降低成本的批量处理的数量生产来制造。

    Apparatus and method for interconnection between a component and a printed circuit board
    119.
    发明申请
    Apparatus and method for interconnection between a component and a printed circuit board 审中-公开
    组件与印刷电路板互连的装置和方法

    公开(公告)号:US20040084210A1

    公开(公告)日:2004-05-06

    申请号:US10625216

    申请日:2003-07-22

    Abstract: A first signal routing layer may be formed on a first surface of a printed circuit board (PCB). An array of interconnections may formed on the first surface of the PCB, the array of interconnections comprising at least one padless via formed within the PCB, the at least one padless via extending from the first signal routing layer to at least one conductive plane and/or a second signal routing layer. The at least one padless via may be in electrical contact with the at least one conductive plane and/or a conductive trace on the second signal routing layer. A component may be attached to the PCB, with a solder interconnection between the at least one padless via and a contact pad on a bottom surface of the component. The component may be, for example, an electronic component such as a ball grid array (BGA) component or a leadless surface mount component.

    Abstract translation: 第一信号布线层可以形成在印刷电路板(PCB)的第一表面上。 互连阵列可以形成在PCB的第一表面上,互连阵列包括形成在PCB内的至少一个无衬垫通孔,从第一信号布线层延伸到至少一个导电平面的至少一个无衬垫通孔和/ 或第二信号路由层。 所述至少一个无衬垫通孔可以与所述至少一个导电平面和/或所述第二信号布线层上的导电迹线电接触。 组件可以附接到PCB,其中焊料互连在该至少一个无衬垫通孔和该部件的底部表面上的接触焊盘之间。 组件可以是例如电子部件,例如球栅阵列(BGA)部件或无引线表面安装部件。

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