公开(公告)号：US20170148723A1

公开(公告)日：2017-05-25

申请号：US15340945

申请日：2016-11-01

Applicant: Intel Corporation

Inventor： Ravindra V. Tanikella

IPC: H01L23/498 ,  H01L23/31 ,  C08K9/10 ,  C08G73/12 ,  C08K3/36 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49894 ,  C08F283/04 ,  C08G73/121 ,  C08K3/36 ,  C08K9/10 ,  C08K2201/011 ,  C08L79/08 ,  C08L2666/66 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/1163 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

公开(公告)号：US09661743B1

公开(公告)日：2017-05-23

申请号：US14565247

申请日：2014-12-09

Applicant: Multek Technologies Ltd.

Inventor： Mark Bergman ,  Joan K. Vrtis

IPC: H05K1/00 ,  H05K1/02 ,  H05K3/46 ,  H05K1/03 ,  H05K1/09

CPC classification number: H01M6/40 ,  A41D1/002 ,  A41D1/005 ,  D05B17/00 ,  H01M2/08 ,  H01M6/12 ,  H01M10/0436 ,  H01R4/00 ,  H01R4/02 ,  H01R4/029 ,  H01R43/005 ,  H01R43/02 ,  H01R43/0235 ,  H05K1/0271 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/038 ,  H05K1/0393 ,  H05K1/09 ,  H05K1/11 ,  H05K1/111 ,  H05K1/112 ,  H05K1/115 ,  H05K1/18 ,  H05K1/181 ,  H05K1/189 ,  H05K3/284 ,  H05K3/30 ,  H05K3/305 ,  H05K3/32 ,  H05K3/4015 ,  H05K3/42 ,  H05K3/4644 ,  H05K7/02 ,  H05K9/009 ,  H05K13/04 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/0162 ,  H05K2201/0287 ,  H05K2201/05 ,  H05K2201/09418 ,  H05K2201/09818

Abstract: A flexible circuit board includes a center “rigid” section, such as a printed circuit stack, and an adjoining flexible multi-layer body that are fabricated from a common interconnect layer. A transition material is included at the interface between the center rigid section and the flexible multi-layer body to minimize ripping and cracking of the interconnect layer. The transition material can also be added at stress areas not related to the interface. The transition material is attached at the interface and stress areas of the flexible circuit board in order to strengthen the flexible circuit board in general and in particular the transition material included therein. The transition material layer is formed and deposited at one or more locations on or within the flexible circuit board in order to minimize, reduce, if not prevent cracking and ripping of the flexible circuit board as it is bent, flexed and/or twisted.

公开(公告)号：US20170077023A1

公开(公告)日：2017-03-16

申请号：US15364143

申请日：2016-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

Abstract translation: 半导体衬底包括：1）具有第一表面和与第一表面相对的第二表面的第一电介质结构; 2）具有与第三表面相对的第三表面和第四表面的第二介电结构，其中第四表面面向第一表面，第二介电结构限定从第三表面延伸到第四表面的通孔，其中腔是 由通孔和第一电介质结构限定; 3）设置在第一介电结构的第一表面上的第一图案化导电层; 以及4）第二图案化导电层，设置在所述第一介电结构的第二表面上并且包括至少一个导电迹线。 第一介电结构限定至少一个开口以暴露第二图案化导电层的一部分。

公开(公告)号：US09565752B1

公开(公告)日：2017-02-07

申请号：US14737268

申请日：2015-06-11

Applicant: AUTOMATED ASSEMBLY CORPORATION

Inventor： Robert Neuman ,  Scott Lindblad

IPC: H01Q1/00 ,  H05K1/02 ,  H01Q1/50 ,  F21V23/00 ,  H05K1/03 ,  H05K1/09 ,  F21K99/00 ,  H05K3/10 ,  H05K3/32 ,  F21Y101/02

CPC classification number: H05K1/028 ,  F21Y2115/10 ,  H01Q1/2208 ,  H01Q7/00 ,  H05K1/032 ,  H05K1/0386 ,  H05K1/0393 ,  H05K1/09 ,  H05K3/103 ,  H05K3/32 ,  H05K2201/0145 ,  H05K2201/0158 ,  H05K2201/10098 ,  H05K2201/10106 ,  H05K2201/10287 ,  H05K2203/049

Abstract: A disclosed circuit arrangement includes a substrate, an integrated circuit (IC) component attached to the substrate, first and second cross wires attached to the substrate and disposed proximate the electronic device, and one or more wire segments attached to the substrate. The one or more wire segments have first and second portions attached at a third portion of the first cross wire and at a fourth portion of the second cross wire, respectively. The first and second cross wires and the one or more wire segments are round wires having round cross sections. The first portion and the third portion have flat areas of contact, and the second and fourth portions have flat areas of contact. A first bond wire is connected to the electronic device and to the first portion of the one or more wire segments, and a second bond wire is connected to the electronic device and to the second portion of the one or more wire segments.

Abstract translation: 所公开的电路装置包括衬底，附着到衬底的集成电路（IC）部件，附接到衬底并设置在电子器件附近的第一和第二交叉线以及附接到衬底的一个或多个线段。 一个或多个线段具有分别在第一十字线的第三部分和第二十字线的第四部分附接的第一和第二部分。 第一和第二十字线和一个或多个线段是具有圆形横截面的圆形线。 第一部分和第三部分具有平坦的接触区域，并且第二和第四部分具有平坦的接触区域。 第一接合线连接到电子设备和一个或多个线段的第一部分，并且第二接合线连接到电子设备和一个或多个线段的第二部分。

公开(公告)号：US20160249451A1

公开(公告)日：2016-08-25

申请号：US15144503

申请日：2016-05-02

Applicant: NOVOSET, LLC

Inventor： Sajal Das ,  Patrick Shipman

IPC: H05K1/03 ,  C08G73/06

CPC classification number: H05K1/0326 ,  B32B15/06 ,  B32B15/20 ,  B32B25/02 ,  B32B2307/204 ,  B32B2457/08 ,  C08F279/02 ,  C08F283/12 ,  C08J5/24 ,  C08J2351/00 ,  C08J2351/08 ,  H05K1/0346 ,  H05K1/0366 ,  H05K2201/015 ,  H05K2201/0158 ,  H05K2201/0162

Abstract: A ultra low loss dielectric thermosetting resin composition has at least one cyanate ester component (A) and at least one reactive intermediate component (B) that is capable of copolymerization with said component (A). The invention is a cyanate ester resin of the form: Tn-[W—(Z)f/(H)1-f—W]n−1—[W—(Z)f/(H)1-f—(OCN)f/(R)1-f]n+2, wherein T is a 1,3,5-substituted-triazine moiety (C3N3); W is a linking atom between triazine and either component A or component B; Z is component (A): H is component (B); OCN is a cyanate ester end group; R is a reactive end group of component B; n is an integer greater than or equal to 1; and f is a weight or mole fraction of component A. The composition exhibits excellent dielectric properties and yields a high performance laminate for use in high layer count, multilayer printed circuit board (PCB), prepregs, resin coated copper (RCC), film adhesives, high frequency radomes, radio frequency (RF) laminates and various composites.

Abstract translation: 超低损耗介电热固性树脂组合物具有至少一种能与所述组分（A）共聚的氰酸酯组分（A）和至少一种反应性中间组分（B）。 本发明是以下形式的氰酸酯树脂：Tn- [W-（Z）f /（H）1-f-W] n-1- [W-（Z）f /（H）1-f-（ OCN）f /（R）1-f] n + 2，其中T是1,3,5-取代三嗪部分（C 3 N 3）; W是三嗪与组分A或组分B之间的连接原子; Z是组分（A）：H是组分（B）; OCN是氰酸酯端基; R是组分B的反应性端基; n是大于或等于1的整数; 并且f是组分A的重量或摩尔分数。组合物显示出优异的介电性能并产生用于高层计数，多层印刷电路板（PCB），预浸料，树脂涂层铜（RCC），膜粘合剂 ，高频雷达，射频（RF）层压板和各种复合材料。

公开(公告)号：US20160174364A1

公开(公告)日：2016-06-16

申请号：US14970479

申请日：2015-12-15

Applicant: Amphenol Corporation

Inventor： Arthur E. Harkness, JR. ,  Eva M. Kenny-McDermott ,  Paul W. Farineau ,  Raymond A. Lavallee ,  Michael Fancher

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/38 ,  H05K3/46 ,  H05K3/00 ,  H05K3/22 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K3/4632 ,  H05K1/0242 ,  H05K1/0326 ,  H05K1/034 ,  H05K1/0346 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/09 ,  H05K1/111 ,  H05K1/115 ,  H05K1/116 ,  H05K3/0073 ,  H05K3/202 ,  H05K3/22 ,  H05K3/38 ,  H05K3/382 ,  H05K3/383 ,  H05K3/384 ,  H05K3/385 ,  H05K3/388 ,  H05K3/389 ,  H05K3/4658 ,  H05K3/4685 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2203/1194

Abstract: High-speed interconnects for printed circuit boards and methods for forming the high-speed interconnects are described. A high-speed interconnect may comprise a region of a conductive film having a reduced surface roughness and one or more regions that have been treated for improved bonding with an adjacent insulating layer. Regions of reduced roughness may be used to carry high data rate signals within PCBs. Regions treated for bonding may include a roughened surface, adhesion-promoting chemical treatment, and/or material deposited to improve wettability of the surface and/or adhesion to a cured insulator.

Abstract translation: 描述了用于印刷电路板的高速互连以及用于形成高速互连的方法。 高速互连可以包括具有减小的表面粗糙度的导电膜的区域和已经被处理以改善与相邻绝缘层的接合的一个或多个区域。 粗糙度降低的区域可用于在PCB内携带高数据速率信号。 用于粘合处理的区域可以包括粗糙表面，促进粘附的化学处理和/或沉积以提高表面的润湿性和/或对固化的绝缘体的粘附的材料。

公开(公告)号：US20150181692A1

公开(公告)日：2015-06-25

申请号：US14136428

申请日：2013-12-20

Applicant: Christopher Jezewski ,  Ravi Pillarisetty ,  Brian Doyle

Inventor： Christopher Jezewski ,  Ravi Pillarisetty ,  Brian Doyle

IPC: H05K1/02 ,  H05K1/03

CPC classification number: H05K1/038 ,  D03D1/0088 ,  D03D11/02 ,  D03D15/00 ,  H05K1/028 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/0058 ,  H05K3/10 ,  H05K3/28 ,  H05K3/284 ,  H05K3/32 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/029

Abstract: A system comprises an article comprising one or more fabric layers, a plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.

Abstract translation: 系统包括包括一个或多个织物层的制品，多个电子装置，每个电子装置并入到一个或多个织物层中的一个或多个织物层之一中，以及多个电子装置中的两个或更多个之间的一个或多个通信连接。 多个电子设备中的每一个可以包括耦合到织物层的柔性衬底，沉积在柔性衬底上的一个或多个金属化层以及电耦合到一个或多个金属化层的一个或多个电子部件。

公开(公告)号：US20150044485A1

公开(公告)日：2015-02-12

申请号：US14170263

申请日：2014-01-31

Applicant: Elite Electronic Material (kunShan) Co., Ltd.

Inventor： Rongtao WANG ,  Chen Yu HSIEH ,  Wenjun TIAN ,  Ziqian MA ,  Wenfeng LV

IPC: H05K1/03

CPC classification number: H05K1/0353 ,  H05K1/0326 ,  H05K2201/0158 ,  Y10T428/31696

Abstract: The present invention provides a resin composition useful for a copper-clad laminate and a printed circuit board, wherein the resin composition comprises the following components: (A) 100 parts by weight of vinyl-containing polyphenylene ether resin; (B) 5 to 50 parts by weight of maleimide; (C) 10 to 100 parts by weight of styrene-butadiene copolymer; and (D) 5 to 30 parts by weight of cyanate ester resin. The present invention also provides a resin composition and an article made therefrom having low dissipation factor at high frequency and excellent thermal resistance and peeling strength and being useful for a copper-clad laminate and a printed circuit board.

Abstract translation: 本发明提供一种用于覆铜层压板和印刷电路板的树脂组合物，其中树脂组合物包含以下组分：（A）100重量份含乙烯基聚苯醚树脂; （B）5〜50重量份的马来酰亚胺; （C）10〜100重量份苯乙烯 - 丁二烯共聚物; 和（D）5-30重量份的氰酸酯树脂。 本发明还提供一种树脂组合物及其制造的制品，其频率低，散热系数低，耐热性和剥离强度高，对于覆铜层压板和印刷电路板也是有用的。

公开(公告)号：US20150044484A1

公开(公告)日：2015-02-12

申请号：US14381784

申请日：2013-03-21

Applicant: MITSUBISHI GAS CHEMICAL COMPANY, INC.

Inventor： Shoichi Ito ,  Michio Yaginuma ,  Naoki Oka ,  Masataka Kudo

IPC: H05K1/03 ,  C08L71/12 ,  C08K3/00 ,  H01B3/42 ,  B32B15/08

CPC classification number: H05K1/0373 ,  B32B5/024 ,  B32B15/08 ,  B32B15/14 ,  B32B27/20 ,  B32B27/285 ,  B32B27/365 ,  B32B27/38 ,  B32B2260/023 ,  B32B2260/046 ,  B32B2262/0276 ,  B32B2264/102 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2307/702 ,  B32B2457/08 ,  C08G59/4014 ,  C08G65/40 ,  C08G65/48 ,  C08J5/24 ,  C08J2371/00 ,  C08K3/00 ,  C08K3/36 ,  C08L63/00 ,  C08L63/04 ,  C08L69/00 ,  C08L71/123 ,  C08L71/126 ,  C08L2203/20 ,  H01B3/427 ,  H05K2201/0158 ,  H05K2201/0209 ,  Y10T428/31678

Abstract: To provide a prepreg that achieves a low dielectric loss tangent, despite the use of a polar solvent.A prepreg produced by impregnating or coating a base material with a varnish comprising an inorganic filler, a polar solvent, and a resin composition principally comprising polyphenylene ether, and subjecting the base material treated to a drying step, wherein the polar solvent content of the prepreg is 3 mass % or less, and a dielectric loss tangent at 10 GHz of a laminated board produced using this prepreg is 0.001-0.007.

Abstract translation: 为了提供尽管使用极性溶剂来实现低介电损耗角正切的预浸料。 通过用包含无机填料，极性溶剂和主要包含聚苯醚的树脂组合物的清漆浸渍或涂覆基材并将经处理的基材进行干燥步骤制备的预浸料，其中预浸料的极性溶剂含量 为3质量％以下，使用该预浸料制作的层压板的10GHz的介电损耗角正切为0.001-0.007。

公开(公告)号：US08796825B2

公开(公告)日：2014-08-05

申请号：US13353217

申请日：2012-01-18

Applicant: Ravindra V. Tanikella

Inventor： Ravindra V. Tanikella

IPC: H01L23/58 ,  H01L23/12 ,  H01L23/52

CPC classification number: H01L23/49894 ,  C08F283/04 ,  C08G73/121 ,  C08K3/36 ,  C08K9/10 ,  C08K2201/011 ,  C08L79/08 ,  C08L2666/66 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/1163 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

Abstract translation: 用于微电子封装的高度可靠的互连。 在一个实施例中，积聚互连中的电介质层具有玻璃化转变温度的等级; 并且稍后施加的电介质层在低于较早施加的电介质层的玻璃化转变温度的温度下被层压。 在一个实施方案中，通过热固化工艺增加了积聚互连中早期施加的介电膜的玻璃化转变温度，以超过用于层压后来施加的电介质膜的温度。 在一个实施方案中，在层压聚酰亚胺材料的膜（例如，通过催化剂的密封剂的光化学或热降解）之后，用嵌入的催化剂形成聚酰亚胺材料以促进交联。 在一个实施例中，阻焊剂开口壁具有通过激光辅助接种产生的可湿性层，使得阻焊剂开口壁之间没有间隙，并且在阻焊剂开口中没有底部填充物。