公开(公告)号：US20090116193A1

公开(公告)日：2009-05-07

申请号：US11969485

申请日：2008-01-04

Applicant: Yu-Hsueh Lin

Inventor： Yu-Hsueh Lin

IPC: H05K7/20 ,  B05D5/12

CPC classification number: H05K7/205 ,  H01L23/3732 ,  H01L2924/0002 ,  H05K1/053 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0323 ,  H05K2203/0315 ,  H01L2924/00

Abstract: A method for manufacturing a substrate board with high efficiency of heat conduction and electrical isolation is disclosed. The method comprises the steps of: providing a substrate layer with an arrangement surface and a heat-dissipating surface; executing an anodic treatment on the arrangement surface and the heat-dissipating surface to respectively form a first anodic treatment layer and a second anodic treatment layer; forming a heat conduction and electrical isolation layer on the second anodic treatment layer; and forming a diamond like carbon (DLC) layer on the heat conduction and electrical isolation layer. The heat expansion coefficient of the substrate layer is greater than that of the second anodic treatment layer, the heat conduction and electrical isolation layer, and the DLC layer in turn.

Abstract translation: 公开了一种用于制造具有高效率的热传导和电隔离的基板的方法。 该方法包括以下步骤：为衬底层提供布置表面和散热表面; 对配置面和散热面进行阳极处理，分别形成第一阳极处理层和第二阳极处理层; 在所述第二阳极处理层上形成导热和电隔离层; 并在导热和电隔离层上形成类金刚石碳（DLC）层。 衬底层的热膨胀系数大于第二阳极处理层，热传导和电隔离层以及DLC层的热膨胀系数。

公开(公告)号：US07504148B2

公开(公告)日：2009-03-17

申请号：US11307854

申请日：2006-02-24

Applicant: Ming-Hang Hwang ,  Yu-Chiang Cheng ,  Chao-Yi Chen ,  Hsin-Lung Kuo ,  Bin-Wei Lee ,  Wei-Chung Hsiao

Inventor： Ming-Hang Hwang ,  Yu-Chiang Cheng ,  Chao-Yi Chen ,  Hsin-Lung Kuo ,  Bin-Wei Lee ,  Wei-Chung Hsiao

IPC: B32B3/00 ,  H05K1/09

CPC classification number: H05K3/28 ,  H05K1/0203 ,  H05K1/0306 ,  H05K1/05 ,  H05K2201/0179 ,  H05K2201/0323 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/30

Abstract: This invention discloses a manufacturing method and a structure for printed circuit boards. The printed circuit boards are often used for supporting electronic components in circuit and conducting the heat from electronic components. The printed circuit board structure includes a laminated structure. The laminated structure comprises an electric conduction layer and an insulation layer. The electric conduction layer can be made of a special thermal conduction material, including a metal and a bracket structure of carbon element. The insulation layer can be made of thermal conduction material as well, combining a bracket structure of carbon element. The bracket structure of carbon element has high thermal conductivity so as to improve the heat conduction efficiency. The corresponding manufacturing method for this thermal conduction material can be made with chemical vapor deposition, physical vapor deposition, electroplating or the other materials preparation method. The bracket structure of carbon element can be coated on a surface of the metal and also can be mixed into the metal.

Abstract translation: 本发明公开了一种印刷电路板的制造方法和结构。 印刷电路板通常用于支持电路中的电子元件并从电子元件传导热量。 印刷电路板结构包括层叠结构。 层叠结构包括导电层和绝缘层。 导电层可以由特殊的导热材料制成，包括金属和碳元素的支架结构。 绝缘层也可以由导热材料制成，结合碳元素的支架结构。 碳元素的支架结构具有高导热性，从而提高导热效率。 该导热材料的相应制造方法可以通过化学气相沉积，物理气相沉积，电镀或其它材料制备方法制备。 碳元素的支架结构可以涂覆在金属的表面上，并且也可以混入金属中。

公开(公告)号：US20090064493A1

公开(公告)日：2009-03-12

申请号：US12255699

申请日：2008-10-22

Applicant: Takashi KARIYA ,  Hironori Tanaka

Inventor： Takashi KARIYA ,  Hironori Tanaka

IPC: H05K3/00

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09827 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2224/05599

Abstract: A printed circuit board including a conductor portion, an insulating layer formed over the conductor portion, a thin-film capacitor formed over the insulating layer and including a first electrode, a second electrode and a high-dielectric layer interposed between the first electrode and the second electrode, and a via-hole conductor structure formed through the second electrode and insulating layer and electrically connecting the second electrode and the conductor portion. The via-hole conductor structure has a first portion in the second electrode and a second portion in the insulating layer. The first portion of the via-hole conductor structure has a truncated-cone shape tapering toward the conductor portion.

Abstract translation: 一种印刷电路板，包括导体部分，在导体部分上形成的绝缘层，形成在绝缘层之上的薄膜电容器，并且包括第一电极，第二电极和介于第一电极和第二电极之间的高电介质层 第二电极和通过第二电极和绝缘层形成的通孔导体结构，并且电连接第二电极和导体部分。 通孔导体结构在第二电极中具有第一部分，在绝缘层中具有第二部分。 通孔导体结构的第一部分具有朝向导体部分逐渐变细的截锥形。

公开(公告)号：US20090001509A1

公开(公告)日：2009-01-01

申请号：US11770690

申请日：2007-06-28

Applicant: Yaojian Lin

Inventor： Yaojian Lin

IPC: H01L27/01 ,  H01L21/77

CPC classification number: H01L27/016 ,  H01L21/77 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09845

Abstract: A circuit system includes: forming a first electrode over a substrate; applying a dielectric layer over the first electrode and the substrate; forming a second electrode over the dielectric layer; and forming a dielectric structure from the dielectric layer with the dielectric structure within a first horizontal boundary of the first electrode.

Abstract translation: 电路系统包括：在衬底上形成第一电极; 在第一电极和衬底上施加电介质层; 在所述电介质层上形成第二电极; 以及在所述第一电极的第一水平边界内从具有所述电介质结构的介电层形成电介质结构。

公开(公告)号：US20080307620A1

公开(公告)日：2008-12-18

申请号：US12213366

申请日：2008-06-18

Applicant: Jung-Won Lee ,  Yul-Kyo Chung ,  In-Hyung Lee ,  Byung-lk Song ,  Seung-Eun Lee

Inventor： Jung-Won Lee ,  Yul-Kyo Chung ,  In-Hyung Lee ,  Byung-lk Song ,  Seung-Eun Lee

IPC: H01G4/008 ,  H01G9/04

CPC classification number: H01G4/12 ,  H01G4/33 ,  H05K1/162 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355

Abstract: Disclosed are an embedded capacitor and a printed circuit board including the same that can minimize the oxidization of a metal layer. A thin-film capacitor can include a first metal electrode film; a barrier layer, formed on the first metal electrode film to include a conductive oxide; a dielectric film, formed on the barrier layer; and a second metal electrode film, formed on the dielectric film. With the present invention, the outstanding characteristic of a ferroelectric thin film can be provided by minimizing the oxidization of a copper film in the heat treatment after forming the ferroelectric thin film on the copper film.

Abstract translation: 公开了一种嵌入式电容器和包括能够最小化金属层的氧化的印刷电​​路板。 薄膜电容器可以包括第一金属电极膜; 阻挡层，形成在所述第一金属电极膜上，以包括导电氧化物; 形成在阻挡层上的电介质膜; 以及形成在电介质膜上的第二金属电极膜。 通过本发明，可以通过在铜膜上形成铁电薄膜后的热处理中使铜膜的氧化最小化来提供铁电薄膜的突出特性。

公开(公告)号：US20080253097A1

公开(公告)日：2008-10-16

申请号：US11969606

申请日：2008-01-04

Applicant: Shuichi KAWANO

Inventor： Shuichi KAWANO

IPC: H05K1/11 ,  H05K1/16

CPC classification number: H05K1/162 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/3436 ,  H05K3/423 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/0733 ,  H01L2924/00

Abstract: An interposer is constructed with a substrate body having first and second through-holes, a capacitor formed by a laminating dielectric layer and a second electrode portion on a first electrode portion, which is structured on inner surfaces of first and second through-holes and on the first surface of the substrate body. An insulation layer is formed by filling insulation material in the space within the first through-hole surrounded by second electrode portion, and a first post passes through the insulation layer, one end being electrically connected to the first electrode portion, while the first post is electrically insulated from the second electrode portion. Furthermore, a second post is formed in the second through-hole, and is connected to the second electrode portion at its peripheral surface while being electrically insulated from the first electrode portion.

Abstract translation: 内插件由具有第一通孔和第二通孔的基板本体构成，电容器由第一电极部分上的叠层电介质层和第二电极部分构成，该第一电极部分构造在第一通孔和第二通孔的内表面上， 衬底主体的第一表面。 通过在由第二电极部包围的第一通孔内的空间内填充绝缘材料形成绝缘层，第一柱通过绝缘层，一端电连接到第一电极部分，而第一柱为 与第二电极部分电绝缘。 此外，第二通孔形成在第二通孔中，并且在与第一电极部分电绝缘的同时在其外周面与第二电极部分连接。

公开(公告)号：US07405366B2

公开(公告)日：2008-07-29

申请号：US11339661

申请日：2006-01-26

Applicant: Takeshi Shioga ,  Yoshikatsu Ishizuki ,  John David Baniecki ,  Kazuaki Kurihara

Inventor： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  John David Baniecki ,  Kazuaki Kurihara

IPC: H05K1/16

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L21/6835 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/141 ,  H05K1/162 ,  H05K3/007 ,  H05K3/4602 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0191 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: An interposer 2 including a base 10 formed of a plurality of resin layers 26, 34, 42, 52, 56; a thin-film capacitor 12 buried in the base 10, including a lower electrode 20, a capacitor dielectric film 22 and an upper electrode 24; a first through-electrode 14b formed through the base 10 and electrically connected to the upper electrode 24 of the thin-film capacitor 12; and a second through-electrode 14a formed through the base 10 and electrically connected to the lower electrode 20 of the thin-film capacitor 12, further including: an interconnection 48 buried in the base 10 and electrically connected to the respective upper electrodes 24 of a plurality of the thin-film capacitors 12, a plurality of the first through-electrodes 14b being electrically connected to the upper electrodes 24 of said plurality of the thin-film capacitors 12 via the interconnection 48, and said plurality of the first through-electrodes 14b being electrically interconnected by the interconnections 48.

Abstract translation: 包括由多个树脂层26,34,42,52,56形成的基座10的插入件2; 埋在基座10中的薄膜电容器12，包括下电极20，电容器电介质膜22和上电极24; 通过基底10形成并与薄膜电容器12的上部电极24电连接的第一贯通电极14b; 以及通过基底10形成并电连接到薄膜电容器12的下部电极20的第二贯通电极14a，还包括：埋入基座10中并电连接到各个上部电极24的互连件48 多个薄膜电容器12，多个第一贯通电极14b经由互连件48与所述多个薄膜电容器12的上部电极24电连接，所述多个第一贯通电极 - 电极14b通过互连48电互连。

公开(公告)号：US20080134499A1

公开(公告)日：2008-06-12

申请号：US12068272

申请日：2008-02-05

Applicant: Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

Inventor： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John David Baniecki ,  Kazuaki Kurihara

IPC: H05K3/46

CPC classification number: H01L23/50 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0733 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599

Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.

Abstract translation: 插入件包括由多个树脂层68,20,32,48形成的基座8; 掩埋在所述多个树脂层的第一树脂层68和所述多个树脂层的第二树脂层20之间的薄膜电容器18a，18b，其包括第一电容器电极12a，12b，第二电容器电极16 与第一电容器电极12a，12b和第二电容器电极16相对，以及形成在第一电容器电极12a，12b和第二电容器电极16之间的相对介电常数为200或更大的电容器电介质膜14 ; 通过基座8形成并电连接到第一电容器电极12a，12b的第一贯通电极77a; 以及通过基底8形成并电连接到第二电容器电极16的第二贯通电极77b。

公开(公告)号：US20080110667A1

公开(公告)日：2008-05-15

申请号：US12016919

申请日：2008-01-18

Applicant: Jin Ahn ,  Cheol Hwang ,  Sung Kim ,  Chang Ryn ,  Suk Cho ,  Ho Jeon

Inventor： Jin Ahn ,  Cheol Hwang ,  Sung Kim ,  Chang Ryn ,  Suk Cho ,  Ho Jeon

IPC: H05K1/09 ,  H05K1/16

CPC classification number: H05K1/162 ,  H01L2924/0002 ,  H05K1/095 ,  H05K3/108 ,  H05K3/244 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09881 ,  Y10S438/957 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A printed circuit board having embedded capacitors includes a double-sided copper-clad laminate including first circuit layers formed in the outer layers thereof, the first circuit layers including bottom electrodes and circuit patterns; dielectric layers formed by depositing alumina films on the first circuit layers by atomic layer deposition; second circuit layers formed on the dielectric layers and including top electrodes and circuit patterns; one-sided copper-clad laminates formed on the second circuit layers; blind via-holes and through-holes formed in predetermined portions of the one-sided copper-clad laminates; and plating layers formed in the blind via-holes and the through-holes. The manufacturing method of the printed circuit board is also disclosed.

Abstract translation: 具有嵌入式电容器的印刷电路板包括：包含形成在其外层中的第一电路层的双面覆铜层压板，所述第一电路层包括底部电极和电路图案; 通过原子层沉积在第一电路层上沉积氧化铝膜而形成的介电层; 形成在电介质层上并包括顶电极和电路图案的第二电路层; 形成在第二电路层上的单面覆铜层压板; 盲孔通孔和形成在单面覆铜层压板的预定部分中的通孔; 以及形成在盲通孔和通孔中的镀层。 还公开了印刷电路板的制造方法。

公开(公告)号：US07358116B2

公开(公告)日：2008-04-15

申请号：US10134951

申请日：2002-04-29

Applicant: Boyd L. Coomer

Inventor： Boyd L. Coomer

IPC: H01L21/44

CPC classification number: H01L21/486 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15312 ,  H05K3/243 ,  H05K3/4602 ,  H05K3/4647 ,  H05K2201/0179 ,  H05K2203/0369 ,  H05K2203/0733

Abstract: A substrate with at least one conductive post formed prior to the formation of an inter-layer dielectric (ILD) coating on the substrate. The conductive post may be formed from a metal layer of the substrate. Additionally, the conductive post may be built up on the substrate.

Abstract translation: 在衬底上形成层间电介质（ILD）涂层之前形成有至少一个导电柱的衬底。 导电柱可以由衬底的金属层形成。 另外，导电柱可以在衬底上构建。