公开(公告)号：US20080230259A1

公开(公告)日：2008-09-25

申请号：US11689641

申请日：2007-03-22

Applicant: Roger Allen Booth Jr. ,  Matthew Stephen Doyle

Inventor： Roger Allen Booth Jr. ,  Matthew Stephen Doyle

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0224 ,  H05K1/0237 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/0393 ,  H05K2201/09318 ,  H05K2201/09681 ,  H05K2201/09736

Abstract: A method and structure are provided for implementing flexible circuits of various electronic packages and circuit applications. A meshed reference plane includes a variable mesh pitch arranged for control of mechanical flexibility. A dielectric core separates a signal layer from the variable pitch meshed reference plane. An electrically conductive coating covers the surface of the variable pitch meshed reference plane yielding substantially constant signal impedance for the signal layer.

Abstract translation: 提供了一种用于实现各种电子封装和电路应用的柔性电路的方法和结构。 网格参考平面包括用于控制机械柔性的可变网格间距。 介质芯将信号层与可变间距网格参考平面分开。 导电涂层覆盖可变间距网格基准平面的表面，产生信号层基本恒定的信号阻抗。

公开(公告)号：US07383629B2

公开(公告)日：2008-06-10

申请号：US10991532

申请日：2004-11-19

Applicant: John M. Lauffer ,  Voya R. Markovich ,  Michael Wozniak

Inventor： John M. Lauffer ,  Voya R. Markovich ,  Michael Wozniak

IPC: H05K3/06 ,  H05K3/38 ,  H05K3/46

CPC classification number: H01L21/4857 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K3/383 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/09318 ,  H05K2203/0353 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T428/12556 ,  Y10T428/12993 ,  H01L2224/0401

Abstract: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided, as is a method of making the substrate.

Abstract translation: 其中两个导电层（例如，电镀铜箔）被结合（例如层压）到电介质层的电路化衬底。 物理地结合到电介质的两个箔表面中的每一个是光滑的（例如，优选通过化学处理），并且在其上包括薄的有机层，而两个箔的外表面也是光滑的（例如，优选也使用化学处理 步）。 这些导电层中的一个可以用作接地或电压平面，而另一个可以用作具有多个单独信号线作为其一部分的信号平面。 还提供了利用这种电路化基板的电气组件和信息处理系统，以及制造基板的方法。

公开(公告)号：US20080075070A1

公开(公告)日：2008-03-27

申请号：US11978810

申请日：2007-10-30

Applicant: Joel Goergen

Inventor： Joel Goergen

IPC: H04L12/50

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: A circuit board comprises signaling through-holes that pass through a plurality of layers, including signal trace and digital ground plane layers, and power reference plane layers. Clearances are set to achieve a desired impedance characteristic for the through-holes. At a power reference plane layer, the clearance is defined around multiple neighboring through-holes.

Abstract translation: 电路板包括通过多个层的信令通孔，包括信号迹线和数字接地层以及功率参考平面层。 设定间隙以实现通孔所需的阻抗特性。 在功率参考平面层上，间隙围绕多个相邻的通孔限定。

公开(公告)号：US07336139B2

公开(公告)日：2008-02-26

申请号：US11588640

申请日：2006-10-27

Applicant: James Leroy Blair ,  Oswin M. Schreiber ,  Jeffrey Thomas Smith

Inventor： James Leroy Blair ,  Oswin M. Schreiber ,  Jeffrey Thomas Smith

IPC: H01P3/08

CPC classification number: H05K1/0219 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01P3/006 ,  H01P3/08 ,  H05K1/0237 ,  H05K1/0393 ,  H05K1/147 ,  H05K3/222 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/10492 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A high speed flexible interconnect cable includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The transmission line structure may be realized as a grounded coplanar waveguide structure. The cable can be coupled to destination components using a variety of connection techniques. The cable can also be terminated with any number of known or standardized connector packages.

Abstract translation: 高速柔性互连电缆包括多个导电层和多个电介质层。 位于导电层上的导电信号迹线与电介质层结合形成一个或多个高速电传输线结构。 传输线结构可以被实现为接地的共面波导结构。 电缆可以使用各种连接技术耦合到目标组件。 电缆也可以用任何数量的已知或标准的连接器封装端接。

公开(公告)号：US20070268087A9

公开(公告)日：2007-11-22

申请号：US10273410

申请日：2002-10-17

Applicant: Timothy Lemke ,  Richard Elco

Inventor： Timothy Lemke ,  Richard Elco

IPC: H01P5/02

CPC classification number: H05K1/024 ,  H01P3/08 ,  H05K1/14 ,  H05K3/10 ,  H05K3/202 ,  H05K2201/044 ,  H05K2201/09318

Abstract: A novel backplane interconnection system that is useful in the telecommunication and data process industries for ultra high speed backplane systems. It is capable of transmitting digital signals with bandwidths of 10 GHz and beyond. The invention provides high performance at a low cost of manufacture. It is suitable for use in a wide variety of system applications. One embodiment of the invention comprises an air dielectric and copper conductor matched impedance transmission line system that interconnects daughter cards in a conventional backplane configuration. The high speed transmission-line structure is continuous through the backplane-daughter card and return path. Such embodiment are also integrated with conventional printed circuit backplanes or be a stand-alone device.

Abstract translation: 一种新颖的背板互连系统，适用于超高速背板系统的电信和数据处理行业。 它能够传输10 GHz及以上带宽的数字信号。 本发明以低成本制造提供高性能。 适用于各种系统应用。 本发明的一个实施例包括在传统背板配置中互连子卡的空气电介质和铜导体匹配阻抗传输线系统。 高速传输线结构通过背板 - 子卡和返回路径是连续的。 这种实施例也与常规印刷电路底板集成或者是独立设备。

公开(公告)号：US20070202307A1

公开(公告)日：2007-08-30

申请号：US11565869

申请日：2006-12-01

Applicant: Byoung-Ha OH ,  Jong-Hoon KIM

Inventor： Byoung-Ha OH ,  Jong-Hoon KIM

IPC: B32B3/00

CPC classification number: H05K1/0253 ,  H05K1/0224 ,  H05K3/4691 ,  H05K2201/09318 ,  H05K2201/09681 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: Disclosed herein is a rigid flexible PCB having openings. The rigid flexible PCB includes a flexible section with flexibility and rigid sections being formed at the edges of the flexible section with mechanical stiffness. The flexible section comprises a flexible plane. The flexible plane comprises a base insulating layer; a wire conducting layer being adhered to one of the top side and the bottom side of the base insulating layer; and a plane conducting layer adhered to the other of the top side and the bottom side of the base insulating layer. The plane conducting layer has a plurality of openings being formed as a mesh structure. According to the rigid flexible PCB of the invention, the flexibility of the flexible section and the characteristic impedance of signal wire traces may be improved.

Abstract translation: 本文公开了具有开口的刚性柔性PCB。 刚性柔性PCB包括具有柔性的柔性部分，并且在柔性部分的边缘处形成具有机械刚度的刚性部分。 柔性部分包括柔性平面。 柔性平面包括基底绝缘层; 导电层粘接到基底绝缘层的顶侧和底侧之一; 以及与基底绝缘层的顶侧和底侧中的另一个粘合的平面导电层。 平面导电层具有形成为网状结构的多个开口。 根据本发明的刚性柔性PCB，可以提高柔性部分的灵活性和信号线迹线的特性阻抗。

公开(公告)号：US20070173086A1

公开(公告)日：2007-07-26

申请号：US10591890

申请日：2005-09-16

Applicant: Claus Schmiederer ,  Michael Haerer ,  Tobias Kuechen

Inventor： Claus Schmiederer ,  Michael Haerer ,  Tobias Kuechen

IPC: H01R13/648

CPC classification number: H02K11/026 ,  H02K11/024 ,  H05K1/0231 ,  H05K2201/0715 ,  H05K2201/09318

Abstract: An interference suppressor (10) for suppressing high-frequency interference emissions of a direct current motor (26) that is drivable in a plurality of stages and/or directions is proposed, having a plurality of capacitors (16) located on a first side (12) of a printed circuit board (14) and having a plurality of first conductor tracks (18), located on the first side (12) of the printed circuit board (14), for putting the various capacitors (16) into contact with a ground terminal (20), and having a first terminal (22) and at least one further terminal (24) for the individual stages of the direct current motor (26), the first terminal (22) and the at least one further terminal (24) being put into contact with a first connection line (48) for the first stage and at least one further connection line (50) for the at least one further stage of the direct current motor (26). The interference suppressor (10) is characterized in that a ground face (34) is located on a further side (32), diametrically opposite the first side (12), of the printed circuit board (14), and the first connection line (48) and the at least one further connection line (50) are fed through in insulated fashion relative to the ground face (34).

Abstract translation: 提出了用于抑制在多个级和/或方向上可驱动的直流电动机（26）的高频干扰发射的干扰抑制器（10），其具有位于第一侧的多个电容器（16） （14）的多个第一导体轨道（18），位于印刷电路板（14）的第一侧（12）上，用于将各种电容器（16）与 接地端子（20），并且具有用于直流电动机（26）的各个级的第一端子（22）和至少一个另外的端子（24），第一端子（22）和至少一个另外的端子 （24）与用于第一级的第一连接线（48）和用于直流电动机（26）的至少另一级的至少一个另外的连接线（50）接触。 干涉抑制器（10）的特征在于，接地面（34）位于与印刷电路板（14）的第一侧（12）直径相对的另一侧（32）上，并且第一连接线 48），并且所述至少一个另外的连接线（50）相对于所述接地面（34）以绝缘方式进给。

公开(公告)号：US20070145543A1

公开(公告)日：2007-06-28

申请号：US11320274

申请日：2005-12-28

Applicant: Xiang Zeng ,  Jiangqi He ,  Dong-Ho Han

Inventor： Xiang Zeng ,  Jiangqi He ,  Dong-Ho Han

IPC: H01L29/40

CPC classification number: H05K3/242 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/0969 ,  H05K2201/09727 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method including modifying a characteristic impedance along a length of a plating bar of a substrate package. An apparatus including a package substrate including a plurality of transmission lines therethrough, a portion of the plurality of transmission lines each including a plating bar coupled thereto, wherein the plating bar comprises portions having different characteristic impedance along its length. A system including a computing device including a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate including a plurality of transmission lines therethrough, a portion of the plurality of transmission lines each including a plating bar coupled thereto, wherein the plating bar comprises portions having different characteristic impedance along its length.

Abstract translation: 一种方法，包括沿衬底封装的电镀条的长度改变特性阻抗。 一种包括包括穿过其中的多个传输线的封装基板的装置，所述多个传输线的一部分各自包括连接到其上的电镀板，其中所述电镀棒包括沿其长度具有不同特征阻抗的部分。 一种包括计算设备的系统，包括微处理器，所述微处理器通过衬底耦合到印刷电路板，所述衬底包括穿过其中的多个传输线，所述多个传输线中的一部分包括与其耦合的电镀板，其中， 电镀棒包括沿其长度具有不同特性阻抗的部分。

公开(公告)号：US20070040626A1

公开(公告)日：2007-02-22

申请号：US11588640

申请日：2006-10-27

Applicant: James Blair ,  Oswin Schreiber ,  Jeffrey Smith

Inventor： James Blair ,  Oswin Schreiber ,  Jeffrey Smith

IPC: H01P3/08

CPC classification number: H05K1/0219 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01P3/006 ,  H01P3/08 ,  H05K1/0237 ,  H05K1/0393 ,  H05K1/147 ,  H05K3/222 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/10492 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A high speed flexible interconnect cable includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The transmission line structure may be realized as a grounded coplanar waveguide structure. The cable can be coupled to destination components using a variety of connection techniques. The cable can also be terminated with any number of known or standardized connector packages.

Abstract translation: 高速柔性互连电缆包括多个导电层和多个电介质层。 位于导电层上的导电信号迹线与电介质层结合形成一个或多个高速电传输线结构。 传输线结构可以被实现为接地的共面波导结构。 电缆可以使用各种连接技术耦合到目标组件。 电缆也可以用任何数量的已知或标准的连接器封装端接。

公开(公告)号：US20070013056A1

公开(公告)日：2007-01-18

申请号：US11362882

申请日：2006-02-28

Applicant: Si-Hoon Lee ,  Eun-Seok Song

Inventor： Si-Hoon Lee ,  Eun-Seok Song

IPC: H01L23/34

CPC classification number: H01L23/552 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/0216 ,  H05K1/113 ,  H05K1/189 ,  H05K2201/0715 ,  H05K2201/09318 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.

Abstract translation: 胶片封装可以包括带布线基板，安装在带布线基板上的半导体芯片，以及设置在半导体芯片和带布线基板之间的模塑料。 带状布线基板可以包括具有上表面和下表面的膜。 通风口可能会穿透电影。 上层金属层可以设置在膜的上表面上并且包括输入端子图案和/或输出端子图案。 输入端子图案可以包括接地端子图案和/或电源端子图案。 下部金属层可以设置在膜的下表面上并且包括接地层和/或功率层。 接地层和功率层可以至少覆盖芯片安装区域。