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    MEMORY CARD SUBSTRATE WITH ALTERNATING CONTACTS
    121.
    发明申请
    MEMORY CARD SUBSTRATE WITH ALTERNATING CONTACTS 有权
    具有交替联系的记忆卡基板

    公开(公告)号：US20040178513A1

    公开(公告)日：2004-09-16

    申请号：US10385174

    申请日：2003-03-10

    Applicant: Everstone Industry Corp.

    Inventor： Chien-Hung Chen

    IPC: H01L021/4763 ,  H01L023/52

    CPC classification number: H01L23/52 ,  H01L2924/0002 ,  H05K1/117 ,  H05K2201/097 ,  H05K2201/09709 ,  H05K2203/1572 ,  H01L2924/00

    Abstract: A memory card substrate includes a first solder pad assembly formed on a top edge of the memory card substrate. The first solder pad assembly has multiple first solder pads equally spaced from each other and multiple first gaps each sandwiched between two adjacent first solder pads. A second solder pad assembly is formed on a bottom edge of the memory card substrate and has multiple second solder pads equally spaced from each other and multiple second gaps each sandwiched between two adjacent second solder pads. Each first solder pad corresponds to one of the second gaps so that the first solder pads are alternately arranged on the top edge relative to the second solder pads on the bottom edge.

    Abstract translation: 存储卡基板包括形成在存储卡基板的顶部边缘上的第一焊盘组件。 第一焊盘组件具有彼此等距间隔的多个第一焊盘，以及分别夹在两个相邻的第一焊盘之间的多个第一间隙。 第二焊盘组件形成在存储卡基板的底部边缘上，并且具有彼此等间隔开的多个第二焊盘和多个第二间隙，每个间隙夹在两个相邻的第二焊盘之间。 每个第一焊盘对应于第二间隙中的一个，使得第一焊盘相对于底部边缘上的第二焊盘交替布置在顶边缘上。

    Coupling adjusting structure for double-tuned circuit
    123.
    发明申请
    Coupling adjusting structure for double-tuned circuit 有权
    双调谐电路的耦合调整结构

    公开(公告)号：US20040058593A1

    公开(公告)日：2004-03-25

    申请号：US10670687

    申请日：2003-09-25

    Inventor： Shigeru Osada

    IPC: H01R009/22

    CPC classification number: H05K1/165 ,  H01F5/003 ,  H01F17/0033 ,  H05K3/222 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/097 ,  H05K2201/10636 ,  H05K2203/171 ,  Y02P70/611

    Abstract: In a coupling adjusting structure for a double-tuned circuit according to the present invention, first and second coils are configured such that a pair of first conductive patterns formed on a first surface of a printed circuit and a corresponding pair of second conductive patterns formed on a second surface of the printed circuit board are connected via corresponding connecting conductors, thereby making the first and second coils low and thin. Also, one end of the first coil and the corresponding end of the second coil are disposed close to each other, a first ground conductive pattern is disposed at least on the first surface of the printed circuit, and a first jumper connected to the first ground conductive pattern is disposed between the first and second coils so as to adjust an inductive coupling of the double-tuned circuit, thereby achieving a coupling adjusting structure for a double-tuned circuit whose inductive coupling is adjustable.

    Abstract translation: 在根据本发明的用于双调谐电路的耦合调整结构中，第一和第二线圈被配置成使得形成在印刷电路的第一表面上的一对第一导电图案和形成在 印刷电路板的第二表面通过相应的连接导体连接，从而使第一和第二线圈变薄和薄。 此外，第一线圈的一端和第二线圈的对应端部彼此靠近设置，第一接地导体图案至少设置在印刷电路的第一表面上，并且第一跳线连接到第一接地 导电图案设置在第一和第二线圈之间，以便调整双调谐电路的电感耦合，从而实现用于电感耦合可调节的双调谐电路的耦合调节结构。

    Planar inductors and method of manufacturing thereof
    124.
    发明授权
    Planar inductors and method of manufacturing thereof 失效
    平面电感器及其制造方法

    公开(公告)号：US06696910B2

    公开(公告)日：2004-02-24

    申请号：US09904014

    申请日：2001-07-12

    Applicant: Peter R. Nuytkens ,  Ilya E. Popeko ,  Joseph M. Kulinets

    Inventor： Peter R. Nuytkens ,  Ilya E. Popeko ,  Joseph M. Kulinets

    IPC: H01F500

    CPC classification number: H05K1/165 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/24 ,  H01F27/2804 ,  H01F27/365 ,  H01F41/02 ,  H01F41/046 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/15153 ,  H05K3/184 ,  H05K3/381 ,  H05K3/4614 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2203/072 ,  Y10T29/4902 ,  Y10T29/49073 ,  Y10T29/49075 ,  Y10T29/49124 ,  Y10T29/4913

    Abstract: A printed circuit board has two layers of printed circuit board dielectric material; a core made of ferromagnetic material between the two layers; and conductive leads on the opposite side of each dielectric layer from the core connected by via holes through both dielectric layers to form a conducting coil around the core. The conductive leads can form two separate coils around the core to form a transformer. A planar conducing sheet can be placed on or between one or more of the printed circuit board's dielectric layers to shield other circuitry on the printed circuit board from magnetic fields generated around the core. The core can be formed at least in part by electroless plating. Electroplating can be used to add a thicker layer of less conductive ferromagnetic material. Ferromagnetic inductive cores can be formed on the surface of a dielectric material by: dipping the surface of the dielectric in a solution containing catalytic metal particles having a slight dipole; and placing the dielectric in a metal salt to cause a layer containing metal to be electrolessly plated upon the dielectric. Plasma etching or other technique can be used before the dipping process to roughen the dielectric's surface to help attract the catalytic particles. This method can be used to form an inductor core on or between one or more dielectric layers of a printed circuit board, of a multichip module, of an integrated circuit, or of a micro-electromechanical device.

    Abstract translation: 印刷电路板具有两层印刷电路板电介质材料; 由两层之间的铁磁材料制成的铁芯; 并且每个电介质层的相对侧上的导电引线与通过两个电介质层的通孔连接的芯体形成围绕芯的导电线圈。 导电引线可以在芯周围形成两个分离的线圈以形成变压器。 平面导电片可以放置在印刷电路板的介电层中的一个或多个之上或之上，以屏蔽印刷电路板上的其它电路与芯周围产生的磁场。 芯可以至少部分地通过无电镀形成。 可以使用电镀来增加较薄的较不导电的铁磁材料层。 可以通过以下步骤在电介质材料的表面上形成铁磁感应芯：将电介质的表面浸入含有具有轻微偶极子的催化金属颗粒的溶液中; 并将电介质放置在金属盐中以使含有金属的层无电镀在电介质上。 在浸渍过程之前可以使用等离子体蚀刻或其它技术来粗糙化电介质的表面以帮助吸引催化剂颗粒。 该方法可以用于在印刷电路板，多芯片模块，集成电路或微机电装置的一个或多个电介质层之间或之上形成电感器芯。

    Method and system for reducing signal skew by switching between multiple signal routing layers
    126.
    发明授权
    Method and system for reducing signal skew by switching between multiple signal routing layers 失效
    用于通过在多个信号路由层之间切换来减少信号偏移的方法和系统

    公开(公告)号：US06681338B1

    公开(公告)日：2004-01-20

    申请号：US09599091

    申请日：2000-06-21

    Applicant: Ravindranath T. Kollipara

    Inventor： Ravindranath T. Kollipara

    IPC: G06F104

    CPC classification number: H05K1/0248 ,  G06F1/10 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/097

    Abstract: Methods and systems for reducing signal skew caused by dielectric material variations within one or more module substrates are described. In one embodiment, an elongate module substrate having a long axis includes multiple signal routing layers supported by the module substrate. Multiple devices, such as memory devices (e.g. DRAMs) are supported by the module substrate and are operably connected with the signal routing layers. Multiple skew-reducing locations (e.g. vias) within the module permit signals that are routed in two or more of the multiple signal routing layers to be switched to a different signal routing layer. The skew-reducing locations can be arranged in at least one line that is generally transverse the long axis of the module substrate. The lines of skew-reducing locations can be disposed at various locations on the module. For example, a line of skew-reducing locations can be disposed proximate the middle of the module to effectively offset skew. Multiple skew-reducing locations can be provided at other locations within the module as well so that the signals are switched multiple different times as they propagate through the module.

    Abstract translation: 描述了用于减少由一个或多个模块基板内的电介质材料变化引起的信号偏斜的方法和系统。 在一个实施例中，具有长轴的细长模块衬底包括由模块衬底支撑的多个信号路由层。 诸如存储器件（例如DRAM）的多个器件由模块衬底支持并且与信号布线层可操作地连接。 模块内的多个偏斜减少位置（例如，过孔）允许在多个信号路由层中的两个或多个路由层中路由的信号被切换到不同的信号路由层。 偏斜减少位置可以布置在通常横向模块基板的长轴的至少一条线中。 偏斜减少位置的线可以设置在模块上的各个位置。 例如，一排偏斜减少位置可以靠近模块的中间设置，以有效地抵消偏移。 也可以在模块内的其他位置提供多个偏斜减少位置，以便信号在传播通过模块时被多次切换。

    Interconnected series of plated through hole vias and method of fabrication therefor
    128.
    发明授权
    Interconnected series of plated through hole vias and method of fabrication therefor 有权
    互连的电镀通孔通孔及其制造方法

    公开(公告)号：US06493861B1

    公开(公告)日：2002-12-10

    申请号：US09473353

    申请日：1999-12-28

    Applicant: Yuan-Liang Li ,  David G. Figueroa

    Inventor： Yuan-Liang Li ,  David G. Figueroa

    IPC: G06F1750

    CPC classification number: H01F17/0033 ,  H01F41/041 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15312 ,  H05K1/115 ,  H05K1/165 ,  H05K3/06 ,  H05K3/42 ,  H05K2201/086 ,  H05K2201/097 ,  H05K2201/1006 ,  H05K2203/0723 ,  H01L2224/0401

    Abstract: A series of plated through hole (PTH) vias are interconnected by traces that alternate between a top surface and a bottom surface of a dielectric board. The PTH vias in the series can be positioned to create a collinear inductive filter, a coil-type inductive filter, or a transformer. Multiple, electrically isolated series of interconnected PTH vias can be used as a multi-phase inductive filter in one embodiment. In another embodiment, multiple series of interconnected PTH vias are electrically connected by a linking portion of conductive material, resulting in a low-resistance inductive filter. Ferromagnetic material patterns can be embedded in the dielectric board to enhance the inductive characteristics of the interconnected via structures. In one embodiment, a closed-end pattern is provided with two series of interconnected vias coiling around the pattern, resulting in an embedded transformer structure. A method of producing an interconnected series of PTH vias includes providing a dielectric board having a series of holes. In some embodiments, the board includes an embedded ferromagnetic material pattern. The holes and the top and bottom surface of the dielectric board have a conductive material thereupon. Portions of the conductive material are selectively removed, resulting in the embedded inductive filter and/or transformer structure.

    Abstract translation: 一系列电镀通孔（PTH）通孔在电介质板的顶表面和底表面之间交替的迹线互连。 该系列中的PTH通孔可以定位成产生共线感应滤波器，线圈型感应滤波器或变压器。 在一个实施例中，多个电隔离的互连PTH通孔系列可用作多相感应滤波器。 在另一个实施例中，多个互连的PTH通孔系列通过导电材料的连接部分电连接，导致低电阻感应滤波器。 铁磁材料图案可以嵌入电介质板中以增强互连通孔结构的感应特性。 在一个实施例中，闭合端图案具有围绕图案卷绕的两系列互连的通孔，从而形成嵌入式变压器结构。 制造互连的PTH通孔系列的方法包括提供具有一系列孔的电介质板。 在一些实施例中，板包括嵌入的铁磁材料图案。 电介质板的孔和顶表面和底表面具有导电材料。 选择性地去除导电材料的部分，从而产生嵌入的感应滤波器和/或变压器结构。

    Crosstalk reduction in constrained wiring assemblies
    129.
    发明授权
    Crosstalk reduction in constrained wiring assemblies 有权
    约束布线组件中的串扰减少

    公开(公告)号：US06433272B1

    公开(公告)日：2002-08-13

    申请号：US09666011

    申请日：2000-09-19

    Applicant: Otto Richard Buhler ,  Charles Grasso

    Inventor： Otto Richard Buhler ,  Charles Grasso

    IPC: H01B700

    CPC classification number: H04B3/32 ,  H05K1/0228 ,  H05K1/0245 ,  H05K2201/097

    Abstract: A wiring apparatus for reducing electromagnetic interference between conductive wires is provided. Wire pairs are incorporated into rigid or flexible printed circuits to precisely control loop alignment and phase differences. This precise alignment helps to cancel radiated electromagnetic fields and reduce voltage polarities induced in nearby wires. In one embodiment, a pair of parallel wires is aligned parallel to a second, twisted pair of wires. In another embodiment, two twisted pairs of wires, with identical loop lengths, are aligned parallel to each other and offset by exactly one half loop length. In a third embodiment, two twisted pairs of wires are aligned parallel to each other, in which one pair has a loop length that is an integer ratio of the other pair.

    Abstract translation: 提供一种用于降低导线之间的电磁干扰的布线装置。 电线对被结合到刚性或柔性印刷电路中，以精确地控制环路对准和相位差。 这种精确对准有助于消除辐射电磁场并减少附近电线中感应的电压极性。 在一个实施例中，一对平行线平行于第二双绞线对排列。 在另一个实施例中，具有相同环路长度的两条双绞线对彼此平行排列并偏移正好一个半环长度。 在第三实施例中，两条双绞线彼此平行排列，其中一对具有作为另一对的整数比的环长度。

    Electronic transformer/inductor devices and methods for making same
    130.
    发明申请
    Electronic transformer/inductor devices and methods for making same 失效
    电子变压器/电感器件及其制造方法

    公开(公告)号：US20020070831A1

    公开(公告)日：2002-06-13

    申请号：US09961789

    申请日：2001-09-24

    Inventor： Philip A. Harding

    IPC: H01F027/28

    CPC classification number: H01F41/046 ,  H01F17/0033 ,  H05K1/165 ,  H05K3/06 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/086 ,  H05K2201/09063 ,  H05K2201/097 ,  H05K2201/10416 ,  Y10S29/016 ,  Y10T29/4902 ,  Y10T29/49073 ,  Y10T29/49075 ,  Y10T29/49165

    Abstract: The present invention relates to the methods of construction for inductive components of, preferably, ferromagnetic materials such as inductors, chokes, and transformers when used as an integral part of the fabrication of PCB's or FLEX's. In one preferred embodiment, holes are formed through a ferromagnetic substrate and plated with conductive material. The arrangement of these holes, and the subsequent design that ensues, will form the inductive components within the plane of the media in which the device is formed; using the substrate for a magnetic core. By using this approach, the inductive components can be miniaturized to physical sizes compatible with the requirements of modem surface mount technology (SMT) for integrated circuitry (IC). This process also allows these components to be fabricated using mass production techniques, thereby avoiding the need to handle discrete devices during the manufacturing process. In another preferred embodiment, a series of thin, concentric high permeability rings are etched on a substrate to provide high permeability transformers and inductors having minimal eddy current effects.

    Abstract translation: 本发明涉及当用作PCB或FLEX的制造的组成部分时，优选地，铁磁材料如电感器，扼流器和变压器的电感元件的构造方法。 在一个优选实施例中，孔通过铁磁基底形成并且镀有导电材料。 这些孔的布置以及随之而来的设计将在其中形成装置的介质的平面内形成感应部件; 使用用于磁芯的基板。 通过使用这种方法，电感元件可以小型化成符合集成电路（IC）调制解调器表面贴装技术（SMT）要求的物理尺寸。 该过程还允许使用大量生产技术来制造这些部件，从而避免了在制造过程中处理分立器件的需要。 在另一个优选实施例中，在衬底上蚀刻一系列薄的，同心的高磁导率环，以提供具有最小涡流效应的高磁导率变压器和电感器。

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