公开(公告)号：US20030137416A1

公开(公告)日：2003-07-24

申请号：US10377188

申请日：2003-02-28

Inventor： Shuzhen Fu ,  David C. Hanley ,  Raymond A. DeBruin ,  Jack R. Grenfell

IPC: G08B013/14

CPC classification number: G07F7/1008 ,  G06F21/86 ,  G06F2221/2143 ,  G06Q20/341 ,  G07F7/082 ,  H01H2239/032 ,  H05K1/0275 ,  H05K1/144 ,  H05K2201/10378 ,  H05K2201/2018 ,  Y04S40/24

Abstract: A security system for electronic circuits (e.g. electronic circuits contained within a secure POS terminal) is provided that is both more tamper resistant, and tamper responsive and less expensive than the prior art epoxy potting. This is achieved by inserting an electrical connector between a first and a second circuit board contained within a case of the POS terminal. The first and the second circuit boards are any type of circuit board known in the art, including both not limited to, rigid circuit boards, flexible circuit boards, printed circuit boards, etc. If the case is opened the connector no longer provides an electrical connection between the first and the second circuit boards, triggering a tamper detection circuit. In some embodiments of the invention, a flexible conductive film is wrapped around the circuit boards and the connector. If a tamperer attempts to penetrate the case of the POS terminal to disable the tamper detection circuit, the circuit on the flexible security film is interrupted, in turn triggering the tamper detection circuit. As a result, the secure POS terminal of the present invention overcomes the limitations of prior art potted terminals. By eliminating the potting process, in fact, the cost of manufacturing the terminal is reduced and there is no need for a special ventilation system. In addition, the circuitry within the terminal can be accessed for repair and maintenance purposes.

Abstract translation: 提供了一种用于电子电路（例如，包含在安全POS终端内的电子电路）的安全系统，其比现有技术的环氧树脂灌封更具抗篡改性和防篡改响应性并且便宜。 这通过在包含在POS终端的壳体内的第一和第二电路板之间插入电连接器来实​​现。 第一和第二电路板是本领域已知的任何类型的电路板，包括但不限于刚性电路板，柔性电路板，印刷电路板等。如果壳体被打开，连接器不再提供电气 第一和第二电路板之间的连接，触发篡改检测电路。 在本发明的一些实施例中，柔性导电膜缠绕在电路板和连接器周围。 如果打印机尝试渗透POS终端的情况以禁用篡改检测电路，则柔性安全膜上的电路被中断，从而触发篡改检测电路。 结果，本发明的安全POS终端克服了现有技术的封装终端的限制。 通过消除灌封过程，实际上降低了终端制造成本，不需要特殊的通风系统。 此外，可以访问终端内的电路以进行维修和维护。

公开(公告)号：US06529027B1

公开(公告)日：2003-03-04

申请号：US09533407

申请日：2000-03-23

Applicant: Salman Akram ,  Alan G. Wood ,  Warren M. Farnworth

Inventor： Salman Akram ,  Alan G. Wood ,  Warren M. Farnworth

IPC: G01R3102

CPC classification number: H05K7/1061 ,  B33Y10/00 ,  B33Y30/00 ,  B33Y80/00 ,  G01R1/0408 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/07378 ,  G01R3/00 ,  H01L23/32 ,  H01L23/49827 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/8114 ,  H01L2224/81385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K1/112 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/049 ,  H05K2201/09472 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/167 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: An interposer including a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, with an interposer substrate. The fence may include edges that are configured to progressively align a semiconductor device with the interposer substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the interposer substrate. Methods for fabricating the fence include the use of stereolithographic and molding processes. When stereolithography is used to fabricate the fence, a machine vision system that includes at least one camera operably associated with a computer may be used to control a stereolithography apparatus and facilitates recognition of the position and orientation of interposer substrates on and around which material is to be applied in one or more layers to form the fence. As a result, the interposer substrates need not be precisely mechanically aligned.

Abstract translation: 一种插入器，其包括接纳半导体器件（例如倒装芯片型半导体器件）与栅介质基板的栅栏。 栅栏可以包括被配置为使半导体器件与插入器衬底逐渐对准的边缘。 挡板还可以包括一个或多个侧向凹入区域，以便于半导体器件与插入器基板的粗略对准。 围栏的制造方法包括使用立体光刻和成型工艺。 当使用立体光刻制造栅栏时，可以使用包括与计算机可操作地相关联的至少一个照相机的机器视觉系统来控制立体光刻设备并且有助于识别材料在其上和周围的插入物基板的位置和取向 应用于一层或多层以形成栅栏。 结果，内插器基板不需要精确地机械对准。

公开(公告)号：US20020190429A1

公开(公告)日：2002-12-19

申请号：US10213029

申请日：2002-08-05

Inventor： Todd O. Bolken

IPC: B29C031/00

CPC classification number: B29C45/02 ,  B29C45/14655 ,  B29C45/1671 ,  G06K19/077 ,  G06K19/07743 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49855 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/117 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/09063 ,  H05K2201/2018 ,  H05K2203/1316 ,  H05K2203/1476 ,  Y10T29/49121 ,  Y10T29/49171 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A semiconductor card includes a printed circuit substrate upon which is mounted a card circuit including one or more semiconductor components such as dice or packages. External contacts link the card circuit to the circuit of another apparatus by removable insertion therein. The substrate is defined by a peripheral opening in a surrounding frame, which may be part of a multiframe strip. The substrate is connected to the frame by connecting segments. The card includes a first plastic casting molded to the substrate and encapsulating the semiconductor components while leaving a peripheral portion of the substrate uncovered. A second plastic casting is molded to the peripheral portion to abut the first plastic casting and form the card periphery. A method for fabricating the semiconductor card is also included.

Abstract translation: 半导体卡包括印刷电路基板，在该印刷电路基板上安装有包括一个或多个半导体部件（例如芯片或封装）的卡电路。 外部触点通过可拆卸插入将卡电路连接到另一设备的电路。 衬底由周围框架中的外围开口限定，其可以是复帧条的一部分。 基板通过连接段连接到框架。 该卡片包括模塑到基底上的第一塑料浇注并封装半导体部件，同时留下未覆盖的基底的周边部分。 第二塑料铸件被模制到周边部分以邻接第一塑料铸件并形成卡周边。 也包括制造半导体卡的方法。

公开(公告)号：US20020176229A1

公开(公告)日：2002-11-28

申请号：US10132586

申请日：2002-04-25

Applicant: INCEP Technologies, Inc.

Inventor： Edward J. Derian ,  Joseph Ted DiBene II ,  David H. Hartke

IPC: H05K007/20 ,  H01L023/48

CPC classification number: G06F1/18 ,  G06F1/182 ,  G06F1/189 ,  H01L23/427 ,  H01L23/433 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/3011 ,  H01R4/64 ,  H01R12/52 ,  H01R12/7082 ,  H01R12/7088 ,  H01R12/721 ,  H05K1/0206 ,  H05K1/0262 ,  H05K1/0263 ,  H05K1/141 ,  H05K1/144 ,  H05K3/301 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/1053 ,  H05K2201/10598 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2201/2036 ,  H01L2924/00

Abstract: A connector for providing power from a first circuit board to a second circuit board. The apparatus comprises a first conductive member, including a first conductive member first end and a first conductive member second end distal from the first end; a second conductive member disposed within the first conductive member, the second conductive member including a second conductor member first end and a second conductor member second end distal from the second conductor member first end; and one or more first circuit board permanent attachment features for electrical coupling with the first circuit board and second circuit board, and one or more disconnectable conduction features for electrically coupling the connector with the second circuit board.

Abstract translation: 一种用于从第一电路板向第二电路板提供电力的连接器。 该装置包括第一导电构件，其包括第一导电构件第一端和远离第一端的第一导电构件第二端; 设置在所述第一导电构件内的第二导电构件，所述第二导电构件包括第二导体构件第一端和远离所述第二导体构件第一端的第二导体构件第二端; 以及用于与第一电路板和第二电路板的电耦合的一个或多个第一电路板永久附接特征，以及用于将连接器与第二电路板电耦合的一个或多个可断开的导电特征。

公开(公告)号：US06472735B2

公开(公告)日：2002-10-29

申请号：US09826621

申请日：2001-04-05

Applicant: Harlan R. Isaak

Inventor： Harlan R. Isaak

IPC: H01L2302

CPC classification number: H05K1/141 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H05K1/144 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/2018

Abstract: A chip stack comprising at least two base layers, each of which includes a base substrate and a first conductive pattern disposed on the base substrate. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers via an anisotropic epoxy. Also included in the chip stack are at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. One of the integrated circuit chips is at least partially circumvented by the interconnect frame and at least partially covered by one of the base layers. The chip stack further comprises a transposer layer comprising a transposer substrate having a third conductive pattern disposed thereon. The first conductive pattern of one of the base layers is electrically connected to the third conductive pattern of the transposer layer via an anisotropic epoxy.

Abstract translation: 一种芯片堆叠，包括至少两个基层，每个基层包括基底基板和设置在基底基板上的第一导电图案。 芯片堆叠还包括至少一个具有布置在其上的第二导电图案的互连框架。 互连框架设置在基底层之间，其中第二导电图案经由各向异性环氧树脂电连接到每个基底层的第一导电图案。 还包括在芯片堆叠中的至少两个集成电路芯片，其电连接到相应的第一导电图案。 集成电路芯片中的一个至少部分地被互连框架绕过并且至少部分地被基底层之一覆盖。 芯片堆叠还包括转置器层，其包括其上布置有第三导电图案的转印器基板。 基底层之一的第一导电图案经由各向异性环氧树脂电连接到转印层的第三导电图案。

公开(公告)号：US06426466B1

公开(公告)日：2002-07-30

申请号：US09501480

申请日：2000-02-09

Applicant: Bruce J. Chamberlin ,  John M. Lauffer ,  James R. Stack

Inventor： Bruce J. Chamberlin ,  John M. Lauffer ,  James R. Stack

IPC: H05K102

CPC classification number: H05K1/0263 ,  H01R12/7088 ,  H05K3/325 ,  H05K3/403 ,  H05K3/4641 ,  H05K2201/0919 ,  H05K2201/10272 ,  H05K2201/2018

Abstract: A printed wiring board structure having peripheral power input. A printed wiring board having internal conductive layers, wherein each internal conductive layer contains a plurality of tabs extending therefrom. Tabs of similar voltage are vertically aligned within the printed wiring board. A frame within which the printed wiring board is mounted is also provided. The frame, having connections mounted within an inner surface of the frame, electrically contacts the tabs along the periphery of the printed wiring board.

Abstract translation: 具有外围电源输入的印刷电路板结构。 一种具有内部导电层的印刷线路板，其中每个内部导电层包含从其延伸的多个翼片。 类似电压的标签在印刷电路板内垂直对齐。 还提供了安装印刷电路板的框架。 具有安装在框架的内表面内的连接的框架沿着印刷线路板的周边与接片电接触。

公开(公告)号：US20020094603A1

公开(公告)日：2002-07-18

申请号：US10092073

申请日：2002-03-06

Inventor： Harlan R. Isaak

IPC: H01L021/44

CPC classification number: H05K1/141 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H05K1/144 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/2018

Abstract: A chip stack comprising at least two base layers, each of which includes a base substrate and a first conductive pattern disposed on the base substrate. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers via an anisotropic epoxy. Also included in the chip stack are at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. One of the integrated circuit chips is at least partially circumvented by the interconnect frame and at least partially covered by one of the base layers. The chip stack further comprises a transposer layer comprising a transposer substrate having a third conductive pattern disposed thereon. The first conductive pattern of one of the base layers is electrically connected to the third conductive pattern of the transposer layer via an anisotropic epoxy.

公开(公告)号：US06400033B1

公开(公告)日：2002-06-04

申请号：US09585506

申请日：2000-06-01

Applicant: Robert F. Darveaux

Inventor： Robert F. Darveaux

IPC: H01L2940

CPC classification number: H01L24/81 ,  H01L23/10 ,  H01L24/75 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/10568 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A method and apparatus for reinforcing the solder connections between a semiconductor device and a substrate includes the provision of a rigid frame having a central opening through it, a planar top surface, a bottom surface opposite and parallel to the top surface, and a thickness between the two surfaces to equal to the height of the solder connections. The top surface of the frame is attached to the bottom surface of the semiconductor device at the peripheral edges thereof and outside of a plurality of input/output terminals thereon. The bottom surface of the frame is attached to the top surface of the substrate. The frame reinforces the solder connections between a C4-mounted semiconductor die or a C5-mounted semiconductor package and a substrate against the stresses acting on the connections with bending of the PCB.

Abstract translation: 一种用于加强半导体器件和衬底之间的焊料连接的方法和装置包括提供刚性框架，其具有通过其的中心开口，平面顶表面，与顶表面相对并平行的底表面， 两个表面等于焊料连接的高度。 框架的顶面在其外围边缘处和其上的多个输入/输出端子的外部附接到半导体器件的底表面。 框架的底面附着到基板的顶面。 该框架加强了C4安装的半导体管芯或C5安装的半导体封装和基板之间的焊接连接，以抵抗作用在PCB上弯曲的连接上的应力。

公开(公告)号：US20010054758A1

公开(公告)日：2001-12-27

申请号：US09826621

申请日：2001-04-05

Inventor： Harlan R. Isaak

IPC: H01L023/02 ,  H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: H05K1/141 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H05K1/144 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/2018

Abstract: A chip stack comprising at least two base layers, each of which includes a base substrate and a first conductive pattern disposed on the base substrate. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers via an anisotropic epoxy. Also included in the chip stack are at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. One of the integrated circuit chips is at least partially circumvented by the interconnect frame and at least partially covered by one of the base layers. The chip stack further comprises a transposer layer comprising a transposer substrate having a third conductive pattern disposed thereon. The first conductive pattern of one of the base layers is electrically connected to the third conductive pattern of the transposer layer via an anisotropic epoxy.

Abstract translation: 一种芯片堆叠，包括至少两个基层，每个基层包括基底基板和设置在基底基板上的第一导电图案。 芯片堆叠还包括至少一个具有布置在其上的第二导电图案的互连框架。 互连框架设置在基底层之间，其中第二导电图案经由各向异性环氧树脂电连接到每个基底层的第一导电图案。 还包括在芯片堆叠中的至少两个集成电路芯片，其电连接到相应的第一导电图案。 集成电路芯片中的一个至少部分地被互连框架绕过并且至少部分地被基底层之一覆盖。 芯片堆叠还包括转置器层，其包括其上布置有第三导电图案的转印器基板。 基底层之一的第一导电图案经由各向异性环氧树脂电连接到转印层的第三导电图案。

公开(公告)号：US20010036066A1

公开(公告)日：2001-11-01

申请号：US09801437

申请日：2001-03-08

Inventor： Joseph T. Dibene II ,  David H. Hartke ,  Edward J. Derian ,  Carl E. Hoge ,  James M. Broder ,  Jose B. San Andres ,  Joseph S. Riel

IPC: H05K001/00

CPC classification number: H05K7/1092 ,  G06F1/18 ,  G06F1/182 ,  G06F1/189 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/3011 ,  H01R4/64 ,  H01R12/52 ,  H05K1/0206 ,  H05K1/0263 ,  H05K1/141 ,  H05K1/144 ,  H05K3/301 ,  H05K3/368 ,  H05K2201/10318 ,  H05K2201/10325 ,  H05K2201/10598 ,  H05K2201/10704 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2201/2036 ,  H01L2924/00

Abstract: A method, apparatus, and article of manufacture for providing power from a first circuit board having a first circuit board first conductive surface and a first circuit board second conductive surface to a second circuit board having a second circuit board first conductive surface and a second circuit board second conductive surface is described. The apparatus comprises a first conductive member, including a first end having a first conductive member surface electrically coupleable to the first circuit board first conductive surface and a second end distal from the first end having a first conductive member second surface electrically coupleable to the second circuit board first surface. The apparatus also comprises a second conductive member, having a second conductive member first surface electrically coupleable to the first circuit board second surface and a second conductive member second surface distal from the second conductive member first surface electrically coupleable to the second circuit board second conductive surface.

Abstract translation: 一种用于从具有第一电路板第一导电表面和第一电路板第二导电表面的第一电路板向具有第二电路板第一导电表面的第二电路板提供电力的方法，装置和制品， 描述了第二导电表面。 该装置包括第一导电构件，其包括具有电耦合到第一电路板第一导电表面的第一导电构件表面的第一端和远离第一端的第二端，具有电耦合到第二电路的第一导电构件第二表面 第一表面。 该装置还包括第二导电构件，其具有电耦合到第一电路板第二表面的第二导电构件第一表面和远离第二导电构件第一表面的第二导电构件第二表面，电耦合到第二电路板第二导电表面 。