公开(公告)号：US12027555B2

公开(公告)日：2024-07-02

申请号：US17333040

申请日：2021-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Yu Hsieh

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14629 ,  H01L27/14636 ,  H01L27/14649

Abstract: An image sensor includes a semiconductor substrate, a first isolation structure, a visible light detection structure, and an infrared light detection structure. The semiconductor substrate has a first surface and a second surface opposite to the first surface in a vertical direction. The first isolation structure is disposed in the semiconductor substrate for defining pixel regions in the semiconductor substrate. The visible light detection structure and the infrared light detection structure are disposed within the same pixel region, and a first portion of the visible light detection structure is disposed between the second surface of the semiconductor substrate and the infrared light detection structure in the vertical direction.

公开(公告)号：US20240215260A1

公开(公告)日：2024-06-27

申请号：US18595376

申请日：2024-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a passivation layer around the MTJ, and a second SOT layer on the first SOT layer and the passivation layer. Preferably, a top surface of the passivation layer is lower than a top surface of the first SOT layer.

公开(公告)号：US12015076B2

公开(公告)日：2024-06-18

申请号：US18092916

申请日：2023-01-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Chang ,  Yao-Hsien Chung ,  Shih-Wei Su ,  Hao-Hsuan Chang ,  Da-Jun Lin ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/7786

Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed on the gate.

公开(公告)号：US12014995B2

公开(公告)日：2024-06-18

申请号：US17369936

申请日：2021-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chin-Chia Yang ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L23/00 ,  H01L21/02 ,  H01L23/522 ,  H01L29/417

CPC classification number: H01L23/562 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02348 ,  H01L23/5226 ,  H01L29/41725

Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.

公开(公告)号：US20240194797A1

公开(公告)日：2024-06-13

申请号：US18444785

申请日：2024-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  CHI REN

IPC: H01L29/792 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833

Abstract: Abstract of Disclosure A control gate is formed on the substrate. A source diffusion region is formed in the substrate and on a first side of the control gate. A select gate is formed on the source diffusion region. The select gate has a recessed top surface. A charge storage structure is formed under the control gate. A first spacer is formed between the select gate and the control gate and between the charge storage structure and the select gate. A wordline gate is formed on a second side of the control gate opposite to the select gate. A second spacer is formed between the wordline gate and the control gate. A drain diffusion region is formed in the substrate and adjacent to the wordline gate.

公开(公告)号：US12010923B2

公开(公告)日：2024-06-11

申请号：US18116305

申请日：2023-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A semiconductor device includes a substrate having a logic region and a memory region, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer disposed on and directly contacting a top surface of the first interlayer dielectric layer. A portion of the top surface of the first interlayer dielectric layer on the memory region is lower than another portion of the top surface of the first interlayer dielectric layer on the logic region. A memory stack structure is disposed in the first interlayer dielectric layer on the memory region. A passivation layer covers a top surface and sidewalls of the memory stack structure and is in direct contact with the second interlayer dielectric layer. An upper contact structure penetrates through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure and directly contacts the memory stack structure.

公开(公告)号：US12009415B2

公开(公告)日：2024-06-11

申请号：US18144811

申请日：2023-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chien-Liang Wu ,  Kuo-Yu Liao

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66462

Abstract: A semiconductor device includes a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, a first mesa isolation on the HEMT region, a HEMT on the first mesa isolation, a second mesa isolation on the capacitor region, and a capacitor on the second mesa isolation. The semiconductor device further includes buffer layer between the substrate, the first mesa isolation, and the second mesa isolation, in which bottom surfaces of the first mesa isolation and the second mesa isolation are coplanar.

公开(公告)号：US20240188306A1

公开(公告)日：2024-06-06

申请号：US18096532

申请日：2023-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang ,  Hsiang-Hung Peng

IPC: H10B63/00

CPC classification number: H10B63/82

Abstract: A resistive memory device includes a dielectric layer, a first via connection structure, a first stacked structure, and a first insulating structure. The first via connection structure is disposed in the dielectric layer. The first stacked structure is disposed on the first via connection structure and the dielectric layer. The first insulating structure penetrates through a portion of the first stacked structure in a vertical direction and divides the first stacked structure into a first cell unit and a second cell unit. The first cell unit and the second cell unit include a first shared bottom electrode, and the first insulating structure is disposed directly on the first shared bottom electrode.

公开(公告)号：US11990539B2

公开(公告)日：2024-05-21

申请号：US17148526

申请日：2021-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/66462

Abstract: A semiconductor device includes a substrate, a semiconductor channel layer, a semiconductor barrier layer, a gate capping layer, a dielectric layer, and a gate electrode. The semiconductor channel layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor channel layer. The gate capping layer is disposed on the semiconductor barrier layer, and the dielectric layer conformally covers the gate capping layer and surrounds the periphery of the gate capping layer. The gate electrode is disposed on the dielectric layer and covers at least one sidewall of the gate capping layer.

公开(公告)号：US20240164224A1

公开(公告)日：2024-05-16

申请号：US18082609

申请日：2022-12-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Jiun CHANG ,  Yu-Huan YEH ,  Chuan-Fu WANG

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H01L45/1253 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616

Abstract: A ReRAM device includes an interlayer dielectric (ILD), a lower conductive plug, a resistance-switching element (RSE) and an upper conductive plug. The ILD has an upper surface. The lower conductive plug is disposed in the ILD, and has a top surface lower than the upper surface. The RSE is disposed above the top surface and electrically contacts with the top surface. The upper conductive plug is disposed above the RSE and electrically contacts with the RSE.