公开(公告)号：US20060277295A1

公开(公告)日：2006-12-07

申请号：US11194614

申请日：2005-08-02

Applicant: Mineyoshi Masuda ,  Norihiro Kobayashi ,  Tomohiro Morimura

Inventor： Mineyoshi Masuda ,  Norihiro Kobayashi ,  Tomohiro Morimura

IPC: G06F15/173

CPC classification number: H04L43/12 ,  G06F11/3447 ,  G06F11/3495 ,  G06F2201/815 ,  G06F2201/86 ,  G06F2201/885 ,  H04L41/042 ,  H04L41/046

Abstract: The monitoring technology capable of reducing total monitoring cost without degrading the monitoring capability in accordance with the configuration of the large-scale service system and quickly comprehending the state of the service system after the configuration change. A monitoring system in which information processing apparatuses constituting the service system are objects to be monitored has a monitoring manager program and a plurality of monitoring agent programs, and objects to be monitored having the same performance characteristics are sorted into the same groups. In each of the groups, parties where monitoring is carried out at a short monitoring interval and parties where the monitoring is carried out at a long monitoring interval are provided. The performance of objects to be monitored in the party of the long monitoring interval is estimated from the performance of the objects to be monitored in the party of the short monitoring interval.

Abstract translation: 监控技术能够降低总体监控成本，而不会根据大型服务体系的配置降低监控能力，并在配置更改后快速了解业务系统的状态。 其中构成服务系统的信息处理装置是要被监视的对象的监视系统具有监视管理程序和多个监视代理程序，并且具有相同性能特征的被监视对象被分类到相同的组中。 在每个组中，提供在短监视间隔进行监视的各方以及以较长监视间隔进行监视的各方。 在长监视间隔的一方中要监视的对象的性能根据短监视间隔的一方要监视的对象的性能进行估计。

公开(公告)号：US20060255988A1

公开(公告)日：2006-11-16

申请号：US11383305

申请日：2006-05-15

Applicant: Gary Swoboda

Inventor： Gary Swoboda

IPC: H03M1/10

CPC classification number: G06F11/3636 ,  G06F11/3457 ,  G06F2201/885

Abstract: The trace logic are separate from the clocks that operate the system logic. This allows the chip to be placed in a special mode where the functional logic is issued one clock. One frame of trace data is generated for each functional clock issued. A valid signal may be implemented changing state when new information is generated. The trace logic, whose clock is free running, detects the change in state in the valid signal. It then processes the trace information presented to it, exporting this information to a trace recorder. When transmission of this information has created sufficient space to accept a new frame of trace information, the empty signal is generated. This causes the clock generation logic to issue another clock to the system logic.

Abstract translation: 跟踪逻辑与操作系统逻辑的时钟分开。 这允许将芯片置于功能逻辑发出一个时钟的特殊模式。 为发出的每个功能时钟生成一帧跟踪数据。 当生成新信息时，可以实现改变状态的有效信号。 时钟自由运行的跟踪逻辑检测有效信号状态的变化。 然后处理提供给它的跟踪信息，将该信息导出到跟踪记录器。 当这种信息的传输创建了足够的空间来接受新的跟踪信息帧时，产生空信号。 这使得时钟产生逻辑向系统逻辑发出另一个时钟。

公开(公告)号：US20060212263A1

公开(公告)日：2006-09-21

申请号：US10992444

申请日：2004-11-18

Applicant: Brian Koehler ,  Brian Vanderpool

Inventor： Brian Koehler ,  Brian Vanderpool

IPC: G21C17/00

CPC classification number: G06F11/3409 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/88 ,  G06F2201/885

Abstract: A circuit and method for using hardware to calculate a first derivative of the number of performance events that occur in a microprocessor during a predetermined period of time. This first derivative indicates a frequency of such performance events, which can be used as either a predictor of future problems or needs, or may be used to invoke a corrective action.

公开(公告)号：US07073032B2

公开(公告)日：2006-07-04

申请号：US10891221

申请日：2004-07-14

Applicant: Trishul Chilimbi

Inventor： Trishul Chilimbi

IPC: G06F12/08

CPC classification number: G06F8/4442 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/3471 ,  G06F12/12 ,  G06F2201/81 ,  G06F2201/885

Abstract: A system and method for analyzing data accesses to determine data accessing patterns is provided. Data address accesses are traced and transformed into Whole Program Data Accesses (WPDAs). WPDAs may then be used to discover higher-level data abstractions, such as hot data blocks. Hot data blocks provide information related to sequences of data addresses that are repeatedly accessed together. Hot data blocks may then be used to improve program performance.

Abstract translation: 提供了一种用于分析数据访问以确定数据访问模式的系统和方法。 跟踪数据地址访问并将其转换为整个程序数据访问（WPA）。 然后可以使用WPDAs来发现更高级别的数据抽象，例如热数据块。 热数据块提供与一起重复访问的数据地址序列相关的信息。 然后可以使用热数据块来提高程序性能。

公开(公告)号：US20060143421A1

公开(公告)日：2006-06-29

申请号：US10749425

申请日：2003-12-31

Applicant: Sreenivas Subramoney ,  Richard Hudson ,  Mauricio Serrano ,  Ali-Reza Adl-Tabatabai

Inventor： Sreenivas Subramoney ,  Richard Hudson ,  Mauricio Serrano ,  Ali-Reza Adl-Tabatabai

IPC: G06F12/00

CPC classification number: G06F11/348 ,  G06F12/0253 ,  G06F12/0269 ,  G06F2201/88 ,  G06F2201/885 ,  Y10S707/99957

Abstract: Techniques are described for optimizing memory management in a processor system. The techniques may be implemented on processors that include on-chip performance monitoring and on systems where an external performance monitor is coupled to a processor. Processors that include a Performance Monitoring Unit (PMU) are examples. The PMU may store data on read and write cache misses, as well as data on translation lookaside buffer (TLB) misses. The data from the PMU is used to determine if any memory regions within a memory heap are delinquent memory regions, i.e., regions exhibiting high numbers of memory problems or stalls. If delinquent memory regions are found, the memory manager, such as a garbage collection routine, can efficiently optimize memory performance as well as the mutators performance by improving the layout of objects in the heap. In this way, memory management routines may be focused based on dynamic and real-time memory performance data.

公开(公告)号：US20060136190A1

公开(公告)日：2006-06-22

申请号：US11300325

申请日：2005-12-15

Applicant: Kohsaku Shibata

Inventor： Kohsaku Shibata

IPC: G06F9/45

CPC classification number: G06F11/3457 ,  G06F2201/885

Abstract: The system performance evaluation method of the present invention confirms the existence of the occurrence of a memory access penalty for each cycle (S101) and executes a CPU model only when a memory access penalty has not occurred (S202).

Abstract translation: 本发明的系统性能评估方法确认每个周期存在存储器访问罚分的情况（S101），并且仅在没有发生存储器访问罚分时才执行CPU模型（S202）。

公开(公告)号：US07050956B2

公开(公告)日：2006-05-23

申请号：US09843930

申请日：2001-04-30

Applicant: Mustafa Uysal ,  Ralph Becker-Szendy ,  Arif Merchant ,  Guillermo Alvarez

Inventor： Mustafa Uysal ,  Ralph Becker-Szendy ,  Arif Merchant ,  Guillermo Alvarez

IPC: G06G7/48

CPC classification number: G06F11/3447 ,  G06F11/3414 ,  G06F2201/885

Abstract: A method predicts performance of a system that includes a plurality of interconnected components defining at least one data flow path. The method references a workload specification for the system. The method models the system using one or more component models. Each component model represents selected one or more of the components. Each component model is arranged in like relationship to the data flow path as the selected one or more of the components represented by the component model. Each component model is (a) a constraint upon the workload specification input to that component model or (b) a transformer of the workload specification input to that component model so as to result in one or more output workload specifications that are input workload specifications to subsequent component models along the data flow path or (c) both a constraint and a transformer. At least one of the component models is a constraint. At least some of the component models along the data flow path operate on the workload specification. In one preferred form, operating on the workload specification involves arranging the component models in a hierarchy corresponding to the data flow path; using the specified workload specification as input to the topmost component model in the hierarchy; and applying one or more of the component models to its input workload specification, starting with the topmost component model and then component models at progressively lower levels in the hierarchy. Output workload specification at one level is input workload specification at the next lower level. If the component model comprises a constraint, the method evaluates whether the input workload specification satisfies or violates the constraint. If the component model comprises a workload specification transform, the method modifies the input workload specification so as to produce one or more output workload specifications.

公开(公告)号：US07043719B2

公开(公告)日：2006-05-09

申请号：US09912173

申请日：2001-07-23

Applicant: Jacob K. Gotwals ,  James C. Abel ,  Nathanael K. Brown ,  Brad D. Hinkle

Inventor： Jacob K. Gotwals ,  James C. Abel ,  Nathanael K. Brown ,  Brad D. Hinkle

IPC: G06F9/44

CPC classification number: G06F11/3419 ,  G06F11/3452 ,  G06F2201/88 ,  G06F2201/885

Abstract: A system and a method of automatically prioritizing and analyzing performance data for one or more system configurations are provided. Performance data is obtained about a system using a first tool. The performance data is sorted by a number of contexts, each context divided into a number of sub-contexts. The performance data for at least one sub-context is automatically prioritized using a pre-determined criteria. An insight is obtained using a second tool for at least one sub-context based on the prioritized performance data. An advice associated with that insight is obtained using the second tool.

公开(公告)号：US06971092B1

公开(公告)日：2005-11-29

申请号：US09939172

申请日：2001-08-24

Applicant: Trishul M. Chilimbi

Inventor： Trishul M. Chilimbi

IPC: G06F9/45

CPC classification number: G06F11/3471 ,  G06F11/3466 ,  G06F12/0862 ,  G06F2201/865 ,  G06F2201/885 ,  G06F2212/6024

Abstract: A system and method for analyzing data accesses to determine data access patterns. Data address accesses are traced and transformed into Whole Program Streams (WPS). WPS may then be used to discover higher-level data abstractions, such as hot data streams and data flow graphs. Hot data streams provide information related to sequences of data addresses that are repeatedly accessed together. Data flow graphs indicate how hot data streams are related and include frequencies of each hot data stream following another. Hot data streams and data flow graphs may be used with pre-fetching and/or cache managers to improve program performance.

Abstract translation: 用于分析数据访问以确定数据访问模式的系统和方法。 跟踪数据地址访问并将其转换为全程序流（WPS）。 然后可以使用WPS来发现较高级别的数据抽象，例如热数据流和数据流图。 热数据流提供与一起重复访问的数据地址序列相关的信息。 数据流图表示热数据流是如何相关的，并且包括每个热数据流之间的频率。 热量数据流和数据流图可以与预取和/或缓存管理器一起使用以改善程序性能。

公开(公告)号：US20050216692A1

公开(公告)日：2005-09-29

申请号：US10845409

申请日：2004-05-12

Applicant: Yasuo Watanabe ,  Yasutomo Yamamoto ,  Kazuhisa Fujimoto

Inventor： Yasuo Watanabe ,  Yasutomo Yamamoto ,  Kazuhisa Fujimoto

IPC: G06F12/08 ,  G06F3/06 ,  G06F12/00 ,  G06F13/10

CPC classification number: G06F11/3471 ,  G06F11/3414 ,  G06F11/3433 ,  G06F11/3485 ,  G06F2201/88 ,  G06F2201/885

Abstract: A storage system having a cluster configuration that prevents a load from concentrating on a certain storage node and enhances access performance is disclosed. The storage system is provided with plural storage adaptors having a cache memory for storing data read/written according to an I/O request from a host and a device for holding the data stored in the cache memory, means for connecting an external storage having a logical device that handles the read/written data and a cache memory to the storage adaptor, means for monitoring and grasping a usage situation of each cache memory of the plural storage adaptors and means for referring to information of the usage situation of each cache memory acquired by the grasping means and selecting any of the storage adaptors so that usage of each cache memory is equalized, and the logical device of the external storage is controlled by the storage adaptor selected by the selection means via connection means.

Abstract translation: 公开了一种具有防止负载集中在某个存储节点上并增强访问性能的集群配置的存储系统。 存储系统具有多个存储适配器，其具有高速缓存存储器，用于存储根据来自主机的I / O请求读/写的数据和用于保存存储在高速缓冲存储器中的数据的设备，用于连接具有 处理读/写数据的逻辑设备和存储适配器的高速缓冲存储器，用于监视和掌握多个存储适配器中的每个高速缓冲存储器的使用情况的装置，以及用于参考获取的每个高速缓冲存储器的使用情况的信息的装置 通过握持装置选择任何存储适配器，使得每个高速缓冲存储器的使用均衡，并且外部存储器的逻辑设备由选择装置经由连接装置选择的存储适配器控制。