公开(公告)号：US20030168249A1

公开(公告)日：2003-09-11

申请号：US10365438

申请日：2003-02-13

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Tatsuya Ito ,  Yukihiro Kimura

IPC: H05K007/06

CPC classification number: H05K3/0052 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0919 ,  H05K2201/09736

Abstract: A wiring board comprising: a metal core substrate shaped like a rectangle in plan view and having a front surface and a rear surface; and a buildup layer comprising an electrically insulating layer and a wiring layer, the buildup layer being formed on the front surface or the rear surface of the metal core substrate, wherein the metal core substrate has an extension formed on its side surface.

Abstract translation: 一种布线板，包括：平面图形状为矩形的金属芯基板，具有前表面和后表面; 以及包括电绝缘层和布线层的堆积层，所述积层在所述金属芯基板的前表面或后表面上形成，其中所述金属芯基板在其侧表面上形成有延伸部。

公开(公告)号：US20030151147A1

公开(公告)日：2003-08-14

申请号：US10371827

申请日：2003-02-21

Applicant: Intel Corporation

Inventor： Chee-Yee Chung ,  David G. Figueroa ,  Robert L. Sankman

IPC: H01L023/48

CPC classification number: H05K1/141 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/366 ,  H05K2201/0919 ,  H05K2201/10446 ,  H05K2201/10454 ,  H05K2201/10674 ,  H05K2201/10719 ,  H01L2224/05599

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract translation: 电子电路封装包括电连接到水平封装部分（图3的306）的垂直封装部分（304，图3）。 垂直封装部分包括与垂直平面平行取向的多个导电层（512,514,516，图5）。 垂直部分的水平顶面（图6中的608）上的第一组接合焊盘（606，图6）可以连接到集成电路（图6的302）的接合焊盘（602，图6）。 3）。 垂直部分的水平底面（图6中的614）上的第二组接合焊盘（612，图6））可以连接到水平封装部分上的接合焊盘（616，图6）。 垂直部分的导电层在第一方向上进行接合焊盘间距转换，并且水平封装部分内的导电结构（906,908,910，图9）在第二方向上执行接合焊盘间距转换。

公开(公告)号：US06539613B1

公开(公告)日：2003-04-01

申请号：US09473281

申请日：1999-12-28

Applicant: Kenneth R. Ulmer

Inventor： Kenneth R. Ulmer

IPC: H01C1706

CPC classification number: H01C17/242 ,  H05K1/092 ,  H05K1/167 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/4053 ,  H05K2201/0919 ,  H05K2201/09563 ,  H05K2203/171 ,  Y10T29/49082 ,  Y10T29/49089 ,  Y10T29/49099 ,  Y10T29/49101

Abstract: A method of forming trimmable resistors, resistor ray be embedded into a substrate. A portion of the resistor may be exposed, by segmenting the substrate, so that the resistor may be trimmed to a desired resistance level. Alternatively, a portion of a resistor may be embedded into a substrate, with another portion of the resistor being disposed on the outer surface of the substrate. The portion of the resistor on the outer surface may be trimmed to adjust the resistance of the resistor to a desired level.

Abstract translation: 一种形成可调电阻器的方法，电阻器射线嵌入到衬底中。 可以通过分割衬底来暴露电阻器的一部分，使得电阻器可以被修整到期望的电阻水平。 或者，电阻器的一部分可以嵌入到衬底中，电阻器的另一部分设置在衬底的外表面上。 可以修剪外表面上的电阻器的部分，以将电阻器的电阻调节到期望的电平。

公开(公告)号：US20030003705A1

公开(公告)日：2003-01-02

申请号：US09897369

申请日：2001-07-02

Applicant: Intel Corporation

Inventor： Chee-Yee Chung ,  David G. Figueroa ,  Robert L. Sankman

IPC: H01L021/44

CPC classification number: H05K1/141 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0298 ,  H05K3/3436 ,  H05K3/366 ,  H05K2201/0919 ,  H05K2201/10446 ,  H05K2201/10454 ,  H05K2201/10674 ,  H05K2201/10719 ,  H01L2224/05599

Abstract: An electronic circuit package includes a vertical package section (304, FIG. 3) electrically connected to a horizontal package section (306, FIG. 3). The vertical package section includes multiple conductive layers (512, 514, 516, FIG. 5) oriented in parallel with a vertical plane. A first set of bond pads (606, FIG. 6) on the vertical section's horizontal top surface (608, FIG. 6) can be connected to the bond pads (602, FIG. 6) of an integrated circuit (302, FIG. 3). A second set of bond pads (612, FIG. 6) on the vertical section's horizontal bottom surface (614, FIG. 6) can be connected to bond pads (616, FIG. 6) on the horizontal package section. The conductive layers of the vertical section perform a bond pad pitch conversion in a first direction, and conductive structures (906, 908, 910, FIG. 9) within the horizontal package section perform a bond pad pitch conversion in a second direction.

Abstract translation: 电子电路封装包括电连接到水平封装部分（图3的306）的垂直封装部分（304，图3）。 垂直封装部分包括与垂直平面平行取向的多个导电层（512,514,516，图5）。 垂直部分的水平顶面（图6中的608）上的第一组接合焊盘（606，图6）可以连接到集成电路（图6的302）的接合焊盘（602，图6）。 3）。 垂直部分的水平底面（图6中的614）上的第二组接合焊盘（612，图6））可以连接到水平封装部分上的接合焊盘（616，图6）。 垂直部分的导电层在第一方向上进行接合焊盘间距转换，并且水平封装部分内的导电结构（906,908,910，图9）在第二方向上执行接合焊盘间距转换。

公开(公告)号：US20020185310A1

公开(公告)日：2002-12-12

申请号：US09876314

申请日：2001-06-07

Inventor： John J. Williamson ,  Kalvin W. Korpela ,  George V. Eleftheriades

IPC: H05K001/11 ,  H01R012/04

CPC classification number: H05K1/0234 ,  H05K1/0218 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/0919 ,  H05K2201/09309

Abstract: Printed circuit boards with relatively high line speeds (for example, about one giga bit per second and above) are increasingly being developed. However, at these high line speeds problems arise with via-induced spurious modes being generated and propagating and reflecting along power or ground planes within the printed circuit board. This is problematic because any active devices which reference power or ground during the presence of such a spurious mode experience a change in the reference potential. This can lead to incorrect data reception or transmission. A resistive coating is applied to the edge of a printed circuit board, directly connected to the ground planes and capacitively connected to the power planes. This resistive coating acts to absorb spurious modes and prevent these from reflecting. In addition, the capacitive connection between the power planes and the resistive coating is enhanced, for example, using metallic flanges. This further improves absorption of spurious modes by the resistive coating.

Abstract translation: 线速度相对较高的打印电路板（例如，每秒大约一千兆比特以上）正在越来越多地开发出来。 然而，在这些高线速度下，产生通孔引起的寄生模式，并沿着印刷电路板内的电源或接地平面传播和反射出现问题。 这是有问题的，因为在存在这种假模式的情况下参考功率或接地的任何有源器件经历参考电位的变化。 这可能导致不正确的数据接收或传输。 电阻涂层施加到印刷电路板的边缘，直接连接到接地层并电容连接到电源层。 该电阻涂层起到吸收杂散模式的作用，并防止它们反射。 此外，电源层和电阻涂层之间的电容连接增强，例如使用金属法兰。 这进一步改善了电阻涂层对寄生模式的吸收。

公开(公告)号：US20020017397A1

公开(公告)日：2002-02-14

申请号：US09887815

申请日：2001-06-22

Inventor： Samuel C. Ramey ,  Alexander W. Barr

IPC: H05K001/11

CPC classification number: H05K3/0044 ,  H01R12/52 ,  H01R12/523 ,  H01R12/714 ,  H01R12/721 ,  H05K1/0219 ,  H05K1/117 ,  H05K3/429 ,  H05K2201/0919 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2203/0228 ,  Y10T29/49165

Abstract: A method is disclosed for establishing signal contacts on a multilayer printed circuit board having alternating ground and signal layers in a stack-up configuration. The signal layers have signal pads and conductive traces leading away from the pads. The method comprises the steps of: a) drilling blind signal holes in the printed circuit board down to signal pads on successive signal layers, b) filling the blind signal holes with conductive material, and c) removing strips of the printed circuit board nearly down to successive signal layers to provide on each signal layer a strip of exposed signal contacts for the conductive traces thereon.

公开(公告)号：US06344616B1

公开(公告)日：2002-02-05

申请号：US09605713

申请日：2000-06-27

Applicant: Sakae Yokokawa

Inventor： Sakae Yokokawa

IPC: H01B700

CPC classification number: H05K1/189 ,  H01B7/00 ,  H05K3/007 ,  H05K3/403 ,  H05K3/4682 ,  H05K2201/0154 ,  H05K2201/0347 ,  H05K2201/09154 ,  H05K2201/0919 ,  H05K2201/10356 ,  H05K2201/10446 ,  H05K2201/10674

Abstract: A cable for use in connection between integrated circuit elements each having terminals. The cable body has an insulator and a plurality of conductors buried in the insulator to have a matrix pattern in section. The cable body has longitudinal end faces as mounting surfaces which are for mounting the integrated circuit elements, respectively. On each of the mounting surfaces, a plurality of conductor pads are formed to connect with the conductors. The conductor pads are connected to the terminals of each of the integrated circuit elements, respectively.

Abstract translation: 用于连接各自具有端子的集成电路元件之间的电缆。 电缆主体具有绝缘体和埋入绝缘体中的多个导体以具有矩阵图案的截面。 电缆体具有分别用于安装集成电路元件的纵向端面作为安装表面。 在每个安装表面上，形成多个导体焊盘以与导体连接。 导体焊盘分别连接到每个集成电路元件的端子。

公开(公告)号：US06320247B2

公开(公告)日：2001-11-20

申请号：US08818994

申请日：1997-03-17

Applicant: Akira Sakamoto

Inventor： Akira Sakamoto

IPC: H01L2348

CPC classification number: H05K3/4092 ,  H01R12/58 ,  H01R12/721 ,  H01R43/205 ,  H05K3/3405 ,  H05K3/4623 ,  H05K2201/09163 ,  H05K2201/0919 ,  H05K2201/09536 ,  H05K2201/1034 ,  H05K2201/10386 ,  H05K2201/10924

Abstract: There is provided a technique of connecting easily the lead terminal to the board of the module. A plurality of clip lead terminals each has at one end thereof clip portions which are connected electrically to connecting terminals by sandwiching an end portion of a board of a module and the connecting terminals formed thereon between clip members of said clip portions and has a lead portion at the other end thereof. The clip lead terminals are arranged so as to be spaced from one another in parallel with one another with the leading edges of the respective clip portions aligned on a straight line. The clip lead terminals are connected to one another through a tie bar and a guide as a connecting portion, respectively, whereby the connecting clip lead terminal 18 is formed as one-body. The lead portions are bent on every other one, leading end portions of the bent lead portions and leading end portions of the non-bent lead portions are in parallel with each other viewing from a side of the board.

Abstract translation: 提供了将引线端子容易地连接到模块的板的技术。 多个夹子引线端子的一端具有通过夹持模块的板的端部而电连接到连接端子的夹持部分，并且形成在其上的连接端子在所述夹持部分的夹子部件之间并具有引线部分 在另一端。 夹子引线端子被布置成彼此平行地彼此分开，各个夹子部分的前缘在直线上对准。 夹子引线端子分别通过连接杆和引导件彼此连接，由此将连接夹引线端子18形成为一体。 引线部分彼此弯曲，弯曲引线部分的前端部分和非弯曲引线部分的前端部分彼此平行，从板的侧面观察。

公开(公告)号：US6005766A

公开(公告)日：1999-12-21

申请号：US651484

申请日：1996-05-22

Applicant: Yoshitaka Muraki

Inventor： Yoshitaka Muraki

IPC: H05K1/00 ,  H05K1/02 ,  H05K3/00 ,  H05K3/46 ,  H05K5/00

CPC classification number: H05K3/4644 ,  H05K1/0284 ,  H05K3/4694 ,  H05K2201/0919 ,  H05K2201/09972 ,  H05K2201/0999 ,  H05K3/0017 ,  H05K3/4623 ,  Y10S428/901

Abstract: A multi-layered printed circuit board (PCB) for use in items of portable electronic equipment which use a housing having a convex-concave part and/or a bent part, includes a PCB section having a uniformly thick PCB, and a resin board formed over the PCB in a part matching the internal space of the housing. By installing the multi-layered PCB having such a configuration within the housing, the internal space of the housing can be efficiently utilized.

Abstract translation: 一种用于使用具有凸凹部分和/或弯曲部分的壳体的便携式电子设备的多层印刷电路板（PCB），包括具有均匀厚的PCB的PCB部分和形成的树脂板 在与PCB的内部空间匹配的部分。 通过将具有这种构造的多层PCB安装在壳体内，可以有效地利用壳体的内部空间。

公开(公告)号：US5857257A

公开(公告)日：1999-01-12

申请号：US858461

申请日：1997-05-19

Applicant: Masaichi Inaba

Inventor： Masaichi Inaba

IPC: G11B5/60 ,  G11B5/48 ,  G11B21/21 ,  H05K1/05 ,  H05K3/00 ,  H05K3/28 ,  H05K3/44

CPC classification number: G11B5/486 ,  H05K3/44 ,  H05K1/056 ,  H05K2201/0919 ,  H05K2203/054 ,  H05K2203/0554 ,  H05K3/0041 ,  H05K3/28 ,  Y10T29/49027

Abstract: A method of manufacturing a magnetic head suspension having a circuit wiring pattern member such that a circuit wiring pattern is formed integral with a suspension via a flexible insulating base member, comprising the steps of: preparing a laminated plate composed of a flexible insulating base member (2), a conductive layer (6 or 3) formed on one surface thereof, and an elastic metal layer (5 or 1) formed on the other surface thereof; forming a desired circuit wiring pattern (3) in the conductive layer (6) of the laminated plate and an elastic suspension (1) in the elastic metal layer (5) thereof simultaneously, in accordance with photo-fabrication method including both-side simultaneous exposure method; forming a bonding metal layer (10) on the circuit wiring pattern (3) by plating; forming a cover coat layer (11) so as to cover the bonding metal layer; further forming a metal mask (13 or 13A) by forming a surface metal layer (12) on the cover coat layer and by etching the surface metal layer (12) or else by forming a mask (14) on the cover coat layer (11) by thin film forming method; removing the cover coat layer (11) and the flexible insulating base member (2) by etching using the metal mask (13 or 13A); removing the metal mask by etching; and bending the elastic metal layer to a desired shape to form the magnetic head suspension.

Abstract translation: 一种制造具有电路布线图案构件的磁头悬架的方法，使得电路布线图案通过柔性绝缘基底构件与悬架形成一体，包括以下步骤：制备由柔性绝缘基底构件 2），在其一个表面上形成的导电层（6或3）和形成在其另一个表面上的弹性金属层（5或1）; 在层叠板的导电层（6）中形成期望的电路布线图案（3）和弹性金属层（5）中的弹性悬浮液（1），同时根据包括两面同时的光制造方法 曝光方法 通过电镀在所述电路布线图案（3）上形成接合金属层（10）; 形成覆盖层（11）以覆盖所述接合金属层; 通过在覆盖层上形成表面金属层（12）并且通过蚀刻表面金属层（12）或者通过在覆盖层（11）上形成掩模（14）来进一步形成金属掩模（13或13A） ）通过薄膜形成方法; 通过使用金属掩模（13或13A）的蚀刻去除覆盖层（11）和柔性绝缘基底构件（2）; 通过蚀刻去除金属掩模; 并将弹性金属层弯曲成所需的形状以形成磁头悬挂液。