公开(公告)号：US06927992B1

公开(公告)日：2005-08-09

申请号：US10707249

申请日：2003-12-01

Applicant: Yao Tung Yen

Inventor： Yao Tung Yen

IPC: G11C5/06 ,  G11C7/10 ,  H05K1/02

CPC classification number: H05K1/025 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1072 ,  H05K1/0245 ,  H05K2201/09254 ,  H05K2201/09727

Abstract: A module board has trace impedances that are matched at trace junctions. An input line that drives a signal to a junction has its impedance adjusted to match the equivalent impedance of branch traces output from the junction. Since input and output impedances match, reflections caused by the junction are minimized or eliminated. The input impedance can match by being within 20% of the equivalent impedance of the branch lines. The equivalent impedance of branches is the reciprocal of the sum of the individual branch lines' reciprocal impedance. Termination can be eliminated when such junctions are impedance-matched. Secondary junctions can also be impedance-matched, allowing for a variety of trace topologies. Such trace-impedance matching is especially useful for memory modules.

Abstract translation: 模块板具有跟踪结点匹配的迹线阻抗。 将信号驱动到接点的输入线的阻抗被调整为匹配从接点输出的分支走线的等效阻抗。 由于输入和输出阻抗匹配，结点引起的反射被最小化或消除。 输入阻抗可以匹配在分支线的等效阻抗的20％以内。 分支的等效阻抗是各个分支线的倒数阻抗之和的倒数。 当这种结点阻抗匹配时，可以消除终止。 二次结也可以是阻抗匹配的，允许各种迹线拓扑。 这种跟踪阻抗匹配对于存储器模块特别有用。

公开(公告)号：US20050158553A1

公开(公告)日：2005-07-21

申请号：US11078342

申请日：2005-03-14

Applicant: Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

Inventor： Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/18 ,  H05K3/24 ,  H05K3/38 ,  H05K3/46 ,  B05D5/12

CPC classification number: H01R9/09 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/0256 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/184 ,  H05K3/241 ,  H05K3/382 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/0594 ,  Y10T29/49155 ,  Y10T29/49194 ,  Y10T428/31504

Abstract: A filet F is added to a portion constituting a corner portion C equal to or smaller than 90° in a crossing portion X of wiring patterns 58b, 58c and 58d, and a wiring pattern 58 is formed. Since the filet F is added, the wiring patterns are not made thin and are not disconnected in the crossing portion X. Further, since there is no stress concentrated to the crossing portion X, disconnection is not caused in the wiring patterns and no air bubbles are left between the crossing portion X of the wiring patterns and an interlayer resin insulating layer so that reliability of a printed wiring board is improved.

Abstract translation: 在布线图案58b，58c和58d的交叉部分X中，将构图F添加到构成等于或小于90°的拐角部分C的部分，并且形成布线图案58。 由于添加了纸张F，所以布线图案不会变薄，并且在交叉部分X中不会断开。另外，由于不会对交叉部分X集中的应力，因此布线图案中不会导致断线，也不会产生气泡 留在布线图案的交叉部分X和层间树脂绝缘层之间，从而提高了印刷线路板的可靠性。

公开(公告)号：US20050001638A1

公开(公告)日：2005-01-06

申请号：US10832700

申请日：2004-04-27

Applicant: Charles Miller ,  John Long

Inventor： Charles Miller ,  John Long

IPC: G01R1/073 ,  H05K1/00 ,  H05K1/02 ,  G01R31/02

CPC classification number: G01R31/31926 ,  G01R1/07378 ,  G01R31/318511 ,  G11C29/56 ,  G11C2029/2602 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0289 ,  H05K2201/09254 ,  Y10T29/49117

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

Abstract translation: 互连结构采用闭合栅格总线将集成电路测试器通道连接到半导体晶片上的输入/输出（I / O）焊盘阵列，使得测试仪通道可以同时与所有I / O焊盘通信。 互连结构包括实现总线节点阵列的电路板，每个总线节点对应于单独的一个I / O焊盘。 电路板包括至少两层。 安装在第一层上的轨迹形成一组第一个菊花链总线，每个链路总线连接总线节点阵列的单独行的所有总线节点。 安装在第二电路板层上的迹线形成一组第二菊花链总线，每条链路总线连接总线节点阵列的单独列的所有总线节点。 第一和第二菊花链总线的通路和其他电路板互连端，使得它们形成闭合栅格总线。 每个总线节点通过单独的隔离电阻器连接到安装在电路板表面上的单独的接触焊盘。 一组弹簧触点或探针将每个接触垫连接到晶片上的单独的I / O焊盘之间。

公开(公告)号：US20040260859A1

公开(公告)日：2004-12-23

申请号：US10883488

申请日：2004-07-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myun-joo Park ,  Byung-se So

IPC: G11C005/00

CPC classification number: H05K1/0216 ,  G06F13/1684 ,  G11C5/04 ,  G11C5/06 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/09254 ,  H05K2201/10159 ,  H05K2203/1572

Abstract: A memory module is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced. As a result, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a board and a module connector can be reduced. The memory module includes a plurality of tabs located in one side of the front and in one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias. At least one memory device is connected to each of the data buses. Preferably, each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.

Abstract translation: 存储器模块能够构成可以减少整个通道的长度的短循环形式的存储器总线系统。 结果，该系统适用于高速操作，并且可以减少制造诸如板和模块连接器的系统的成本。 存储器模块包括位于存储器模块的前部和后侧的一侧中的多个突片，用于通过系统板上的连接器互连，用于连接两个不同信号层的多个通孔 存储器模块和多个数据总线通过每个通孔从存储器模块的前面的突出部延伸到存储器模块的后部上的突出部。 至少一个存储器件连接到每个数据总线。 优选地，每个数据总线形成为垂直于其上形成有突片的存储器模块的一侧。

公开(公告)号：US20040201405A1

公开(公告)日：2004-10-14

申请号：US10797941

申请日：2004-03-11

Inventor： Abdallah Bacha ,  Maksim Kuzmenka ,  Simon Muff ,  Siva Raghuram

IPC: H03L007/00

CPC classification number: G11C7/1066 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03K5/1506 ,  H03L7/06 ,  H03L7/07 ,  H05K1/0237 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/10159 ,  Y02P70/611

Abstract: A circuit module has a circuit board, multiple circuit units on the circuit board and at least one clock input on the circuit board for receiving an external clock signal. The circuit module has a first PLL unit on the circuit board for providing an internal clock signal based on the external clock signal to at least a first one of the circuit units. In addition, the circuit module has a second PLL unit on the circuit board for providing an internal clock signal based on the external clock signal to at least a second one of the circuit units.

Abstract translation: 电路模块具有电路板，电路板上的多个电路单元和用于接收外部时钟信号的电路板上的至少一个时钟输入。 电路模块在电路板上具有第一PLL单元，用于基于外部时钟信号向至少第一个电路单元提供内部时钟信号。 此外，电路模块在电路板上具有第二PLL单元，用于基于外部时钟信号向至少第二电路单元提供内部时钟信号。

公开(公告)号：US06784677B2

公开(公告)日：2004-08-31

申请号：US10406669

申请日：2003-04-02

Applicant: Charles A. Miller ,  John Matthew Long

Inventor： Charles A. Miller ,  John Matthew Long

IPC: G01R1073

CPC classification number: G01R31/31926 ,  G01R1/07378 ,  G01R31/318511 ,  G11C29/56 ,  G11C2029/2602 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0289 ,  H05K2201/09254 ,  Y10T29/49117

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

Abstract translation: 互连结构采用闭合栅格总线将集成电路测试器通道连接到半导体晶片上的输入/输出（I / O）焊盘阵列，使得测试仪通道可以同时与所有I / O焊盘通信。 互连结构包括实现总线节点阵列的电路板，每个总线节点对应于单独的一个I / O焊盘。 电路板包括至少两层。 安装在第一层上的轨迹形成一组第一个菊花链总线，每个链路总线连接总线节点阵列的单独行的所有总线节点。 安装在第二电路板层上的迹线形成一组第二菊花链总线，每条链路总线连接总线节点阵列的单独列的所有总线节点。 第一和第二菊花链总线的通路和其他电路板互连端，使得它们形成闭合栅格总线。 每个总线节点通过单独的隔离电阻器连接到安装在电路板表面上的单独的接触焊盘。 一组弹簧触点或探针将每个接触垫连接到晶片上的单独的I / O焊盘之间。

公开(公告)号：US06743985B1

公开(公告)日：2004-06-01

申请号：US10370164

申请日：2003-02-19

Applicant: Michael C. Greim ,  Patrick W. Carrier

Inventor： Michael C. Greim ,  Patrick W. Carrier

IPC: H05K706

CPC classification number: H05K1/0216 ,  H05K1/0219 ,  H05K2201/09236 ,  H05K2201/09254

Abstract: A method and apparatus for decreasing crosstalk between conductors, particularly differential pairs, that are routed in high-density patterns on printed circuit boards system. In one embodiment of the invention, a single-ended conductor is divided at a first point into two single-ended conductors of equal width, with the two single-ended conductors being routed around and alongside a differential pair of conductors. Equal and opposite noise is coupled onto each branch of the single-ended signal from each side of the differential pair. The two single-ended conductors are rejoined at a second point to form a combined single-ended conductor. Signals traveling along the two separate paths of the single-ended are combined at the second point and noise carried in the respective signals is cancelled. Noise coupled into the differential pair from the two single-ended paths is eliminated at the receiving end as common mode noise. In other embodiments of the present invention, the single-ended conductors and the differential pairs are oriented between two planes in stripline or dual stripline configurations. The method and apparatus of the present invention can be implemented in numerous media, such as vias and cables (including flex and ribbon).

Abstract translation: 一种减少在印刷电路板系统上以高密度图案布线的导体之间的串扰的方法和装置，特别是差分对。 在本发明的一个实施例中，单端导体在第一点被分成两个相等宽度的单端导体，两个单端导体绕差分对导体路由。 相等和相反的噪声从差分对的每一侧耦合到单端信号的每个分支上。 两个单端导体在第二个点处重新连接以形成组合的单端导体。 在第二点处组合沿着单端两个独立路径行进的信号，并取消相应信号中携带的噪声。 耦合到两个单端路径的差分对的噪声在接收端被消除为共模噪声。 在本发明的其它实施例中，单端导体和差分对在带状线或双带状线构造的两个平面之间取向。 本发明的方法和装置可以在许多介质中实现，例如通孔和电缆（包括柔性和带状物）。

公开(公告)号：US06633207B1

公开(公告)日：2003-10-14

申请号：US09556120

申请日：2000-04-19

Applicant: Seiji Hidaka ,  Michiaki Ota ,  Shin Abe

Inventor： Seiji Hidaka ,  Michiaki Ota ,  Shin Abe

IPC: H01P1213

CPC classification number: H01P3/081 ,  H01P1/203 ,  H01P1/2039 ,  H01P7/082 ,  H05K1/0239 ,  H05K1/0242 ,  H05K2201/09254 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09781

Abstract: A transmission line, a resonator, a filter, a duplexer, and a communication apparatus efficiently minimize power losses due to edge effects, thereby having superior loss-reduction characteristics. A continuous line and a plurality of thin lines each having a predetermined length and branching from both sides of the continuous line are formed on a dielectric substrate. With this structure, edges of the individual thin lines substantially do not exist, so that losses due to edge effects can be efficiently minimized.

Abstract translation: 传输线，谐振器，滤波器，双工器和通信设备有效地最小化由于边缘效应引起的功率损耗，从而具有优异的损耗降低特性。 在电介质基板上形成连续线和多条细长线，每条细长线具有预定长度并从连续线的两侧分支。 利用这种结构，单个细线的边缘基本上不存在，从而可以有效地最小化由于边缘效应引起的损耗。

公开(公告)号：US06542048B1

公开(公告)日：2003-04-01

申请号：US09548686

申请日：2000-04-13

Applicant: James R. Sherman ,  Elvin C. Chou

Inventor： James R. Sherman ,  Elvin C. Chou

IPC: H01P512

CPC classification number: H05K1/0234 ,  H01P5/16 ,  H05K1/0237 ,  H05K1/0272 ,  H05K2201/0715 ,  H05K2201/09254 ,  H05K2201/10022

Abstract: A suspended transmission line with an embedded signal channeling device includes a support layer and a conductor supported by the support layer between first and second plates each having a ground plane. The conductor includes a combined signal line and a plurality of discrete signal lines extending from the combined signal line. The discrete signal lines each transmit a portion of a signal transmitted on the combined signal line. A propagation structure is disposed between the first and second plates to substantially contain an electromagnetic field generated by the propagating signal.

公开(公告)号：US20030031001A1

公开(公告)日：2003-02-13

申请号：US10118004

申请日：2002-04-09

Applicant: CHI MEI OPTOELECTRONICS CORP.

Inventor： Chun Yen Chu

IPC: G02F001/1345

CPC classification number: G02F1/13452 ,  H01R12/7076 ,  H01R12/721 ,  H05K1/118 ,  H05K1/147 ,  H05K3/361 ,  H05K2201/09254

Abstract: A flat panel display comprising a display panel, and a first and second printed circuit boards connected to the display panel. The first printed circuit board has a connector. The second printed circuit board comprises a core layer having a main body and a branch extending from the main body. The branch has a terminal portion. A plurality of electrically conductive leads are formed on the surface of the main body and extends to the terminal portion. The terminal portion of the branch including the conductive leads formed thereon is directly inserted into the connector of the first printed circuit board.

Abstract translation: 一种平板显示器，包括显示面板和连接到显示面板的第一和第二印刷电路板。 第一印刷电路板具有连接器。 第二印刷电路板包括具有主体和从主体延伸的分支的芯层。 分支具有端子部分。 多个导电引线形成在主体的表面上并延伸到端子部分。 包括形成在其上的导电引线的分支的端子部分直接插入第一印刷电路板的连接器中。