公开(公告)号：US08581388B2

公开(公告)日：2013-11-12

申请号：US12976427

申请日：2010-12-22

Applicant: Shinnosuke Maeda ,  Tetsuo Suzuki ,  Atsuhiko Sugimoto ,  Tatsuya Ito ,  Takuya Hando ,  Satoshi Hirano

Inventor： Shinnosuke Maeda ,  Tetsuo Suzuki ,  Atsuhiko Sugimoto ,  Tatsuya Ito ,  Takuya Hando ,  Satoshi Hirano

IPC: H01L23/053 ,  H01L21/4763

CPC classification number: H05K3/3452 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/383 ,  H05K3/4682 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/09527 ,  H05K2201/099 ,  H05K2203/0346 ,  H05K2203/0369 ,  H01L2924/00

Abstract: A multilayered wiring substrate, comprising: a plurality of first main surface side connecting terminals arranged in a first main surface of a stack structure; and a plurality of second main surface side connecting terminals being arranged in a second main surface of the stack structure; wherein a plurality of conductor layers are alternately formed in a plurality of stacked resin insulation layers and are operably connected to each other through via conductors tapered such that diameters thereof are widened toward the first or the second main surface, wherein a plurality of openings are formed in an exposed outermost resin insulation layer in the second main surface, and terminal outer surfaces of the second main surface side connecting terminals arranged to match with the plurality of the openings are positioned inwardly from an outer main surface of the exposed outermost resin insulation layer, and edges of terminal inner surfaces are rounded.

Abstract translation: 一种多层布线基板，包括：布置在堆叠结构的第一主表面中的多个第一主表面侧连接端子; 并且多个第二主表面侧连接端子布置在所述堆叠结构的第二主表面中; 其中多个导体层交替地形成在多个堆叠的树脂绝缘层中，并且通过锥形的通孔导体可操作地连接，使得其直径朝向第一或第二主表面加宽，其中形成多个开口 在第二主表面中暴露的最外层树脂绝缘层中，并且布置成与多个开口相匹配的第二主表面侧连接端子的端子外表面从暴露的最外层树脂绝缘层的外主表面位于内侧， 并且端子内表面的边缘是圆形的。

公开(公告)号：US20130213699A1

公开(公告)日：2013-08-22

申请号：US13857167

申请日：2013-04-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shunsuke CHISAKA

IPC: H05K1/18 ,  H05K3/32

CPC classification number: H05K1/185 ,  H05K1/182 ,  H05K1/186 ,  H05K3/32 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/09527 ,  H05K2201/09781 ,  H05K2203/063 ,  Y10T29/49139

Abstract: A substrate includes a built-in component that suppresses resin flow occurring in the case of thermocompression bonding in a region where vias and wiring conductors are provided and that reduces the occurrence of via defects and wiring-conductor defects. The resin flow occurring in an outer side portion of a frame-shaped electrode is suppressed in the case of thermocompression bonding by encircling the periphery of a built-in component with the frame-shaped electrode. Because of this structure, the occurrence of defects in vias and wiring conductors arranged in an outer side portion of the frame-shaped electrode may be reduced.

Abstract translation: 基板包括抑制在设置有通孔和布线导体的区域中的热压接时发生的树脂流动并且减少了通孔缺陷和布线导体缺陷的发生的内置部件。 在通过用框状电极环绕内置部件的周围的热压接的情况下，在框状电极的外侧部分发生的树脂流被抑制。 由于这种结构，可以减少布置在框架状电极的外侧部分中的通孔和布线导体中的缺陷的发生。

公开(公告)号：US20130164440A1

公开(公告)日：2013-06-27

申请号：US13776024

申请日：2013-02-25

Applicant: Ibiden Co., Ltd.

Inventor： Masahiro Kaneko ,  Satoru Kose ,  Hirokazu Higashi

IPC: H05K3/00

CPC classification number: H05K3/42 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/115 ,  H05K3/007 ,  H05K3/108 ,  H05K3/22 ,  H05K3/388 ,  H05K2201/0344 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/1377 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a printed wiring board includes forming a removable layer on a support substrate, forming an interlayer resin insulation layer on the removable layer, forming a penetrating hole in the interlayer resin insulation layer, forming a first conductive layer on the interlayer resin insulation layer and on a side wall of the penetrating hole, forming a conductive circuit on the interlayer resin insulation layer, forming a via conductor in the penetrating hole, removing the support substrate from the interlayer resin insulation layer by using the removable layer, forming a protruding portion of the via conductor protruding from a surface of the interlayer resin insulation layer, and forming a surface-treatment coating on a surface of the protruding portion of the via conductor.

Abstract translation: 一种制造印刷电路板的方法，包括在支撑基板上形成可移除层，在可移除层上形成层间树脂绝缘层，在层间树脂绝缘层中形成贯通孔，在层间树脂绝缘层上形成第一导电层 在所述贯通孔的侧壁上形成导电电路，在所述层间树脂绝缘层上形成导通电路，在所述贯通孔中形成通路导体，使用所述可移除层从所述层间树脂绝缘层除去所述支撑基板， 所述通孔导体的一部分从所述层间树脂绝缘层的表面突出，并且在所述通孔导体的所述突出部分的表面上形成表面处理涂层。

公开(公告)号：US20120306608A1

公开(公告)日：2012-12-06

申请号：US13414861

申请日：2012-03-08

Applicant: Yoshinori TAKENAKA

Inventor： Yoshinori TAKENAKA

IPC: H01F5/00 ,  H05K3/30

CPC classification number: H05K3/30 ,  H05K1/0233 ,  H05K1/165 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09527 ,  H05K2201/09672 ,  Y10T29/49021 ,  Y10T29/4913

Abstract: A wiring board includes a core structure having a first surface and a second surface on the opposite side of the first surface, a first buildup structure formed on the first surface of the core structure and including insulation layers, and a second buildup structure formed on the second surface of the core structure and including insulation layers and an inductor device. The insulation layers in the second buildup structure have the thicknesses which are thinner than the thicknesses of the insulation layers in the first buildup structure, and the inductor device in the second buildup structure is position on the second surface of the core structure and includes at least a portion of a conductive pattern formed in the core structure.

Abstract translation: 布线基板包括具有在第一表面的相对侧的第一表面和第二表面的芯结构，形成在芯结构的第一表面上并且包括绝缘层的第一堆积结构，以及形成在第一堆积结构上的第二堆积结构 芯结构的第二表面并包括绝缘层和电感器件。 第二堆积结构中的绝缘层具有比第一堆积结构中的绝缘层的厚度薄的厚度，并且第二堆叠结构中的电感器件位于芯结构的第二表面上并且至少包括 形成在芯结构中的导电图案的一部分。

公开(公告)号：US08188375B2

公开(公告)日：2012-05-29

申请号：US11603884

申请日：2006-11-22

Applicant: Kenichi Kawabata ,  Takaaki Morita

Inventor： Kenichi Kawabata ,  Takaaki Morita

IPC: H05K1/16

CPC classification number: H05K3/4652 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2224/2518 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/185 ,  H05K3/0044 ,  H05K3/0058 ,  H05K3/4602 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/0358 ,  H05K2201/09518 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/0554 ,  H05K2203/1105 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T29/49128 ,  Y10T428/24917 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A multilayer circuit board comprises core layers 101 and 102 made of a core material impregnated with resin, resin layers 111 and 112 interposed between the core layers 101 and 102, a wiring pattern 140 embedded in the resin layers 111 and 112. The core layers 101 and 102 have a thickness of 100 μm or smaller, whereby the entire board can significantly be thinned. Furthermore, the less strong resin layers 111 and 112 are interposed between the hard core layers 101 and 102, whereby the entire board has increased strength.

Abstract translation: 多层电路板包括由浸渍有树脂的芯材制成的芯层101和102，插入在芯层101和102之间的树脂层111和112，嵌入在树脂层111和112中的布线图案140.芯层101 102的厚度为100μm以下，从而能够使整个基板变薄。 此外，较不强的树脂层111和112插入在硬芯层101和102之间，由此整个板具有增加的强度。

公开(公告)号：US20110180307A1

公开(公告)日：2011-07-28

申请号：US12914378

申请日：2010-10-28

Applicant: Nobuyuki NAGANUMA ,  Michimasa Takahashi ,  Masakazu Aoyama

Inventor： Nobuyuki NAGANUMA ,  Michimasa Takahashi ,  Masakazu Aoyama

IPC: H05K1/02 ,  H05K3/10

CPC classification number: H05K3/4691 ,  H05K2201/09527 ,  H05K2201/096

Abstract: A flex-rigid wiring board having a flexible wiring board, a first insulation layer positioned adjacent to a side of the flexible board and having a first hole which penetrates through the first layer, a second insulation layer laminated over the flexible board and the first layer and having a second hole which penetrates through the second layer, the second hole of the second layer being formed along the axis of the first hole of the first layer, a first conductor structure formed in the first hole and including a filled conductor formed by filling plating in the first hole, and a second conductor structure formed in the second hole and including a filled conductor formed by filling plating in the second hole, the second conductor structure being formed along the axis of the first conductor structure and electrically connected to the first conductor structure.

Abstract translation: 一种具有柔性布线板的挠性刚性布线板，与柔性板的一侧相邻并且具有穿过第一层的第一孔的第一绝缘层，层压在柔性板上的第二绝缘层和第一层 并且具有穿过所述第二层的第二孔，所述第二层的第二孔沿着所述第一层的第一孔的轴线形成，形成在所述第一孔中的第一导体结构，所述第一导体结构包括填充导体， 电镀在第一孔中，第二导体结构形成在第二孔中，并且包括通过在第二孔中填充电镀形成的填充导体，第二导​​体结构沿着第一导体结构的轴线形成并电连接到第一孔 导体结构。

公开(公告)号：US07943863B2

公开(公告)日：2011-05-17

申请号：US11882198

申请日：2007-07-31

Applicant: Junichi Nakamura

Inventor： Junichi Nakamura

IPC: H05K1/11

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K3/108 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09527 ,  Y10T29/4913 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A wiring substrate includes a first insulation layer, a connection terminal, a second insulation layer, a via, and a wiring pattern. The connection terminal is disposed in the first insulation layer so as to be exposed from a first main surface of the first insulation layer, and is electrically connected with a semiconductor chip. The second insulation layer is disposed on a second main surface of the first insulation layer situated on the opposite side from the first main surface. The via is disposed in the second insulation layer, and is electrically connected with the connection terminal. The via is separated from the connection terminal. The wiring pattern is disposed on the second main surface of the first insulation layer and electrically connects the connection terminal and the via.

Abstract translation: 布线基板包括第一绝缘层，连接端子，第二绝缘层，通孔和布线图案。 连接端子设置在第一绝缘层中，以从第一绝缘层的第一主表面露出，并与半导体芯片电连接。 第二绝缘层设置在位于与第一主表面相反一侧的第一绝缘层的第二主表面上。 通孔设置在第二绝缘层中，并与连接端子电连接。 通孔与连接端子分离。 布线图案设置在第一绝缘层的第二主表面上，并且电连接连接端子和通孔。

公开(公告)号：US20110108947A1

公开(公告)日：2011-05-12

申请号：US12590650

申请日：2009-11-12

Applicant: John S. Guzek ,  Mihir K. Roy ,  Brent M. Roberts

Inventor： John S. Guzek ,  Mihir K. Roy ,  Brent M. Roberts

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H05K1/165 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0254 ,  H05K1/0262 ,  H05K1/116 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/1572 ,  H01L2924/00

Abstract: A microelectronic device comprises a first substrate (110) having a first electrically conductive path (111) therein and a second substrate (120) above the first substrate and having a second electrically conductive path (121) therein, wherein the first electrically conductive path and the second electrically conductive path are electrically connected to each other and form a portion of a current loop (131) of an inductor (130).

Abstract translation: 微电子器件包括其中具有第一导电路径（111）的第一衬底（110）和在第一衬底上方的第二衬底（120），并且其中具有第二导电路径（121），其中第一导电路径和 第二导电路径彼此电连接并形成电感器（130）的电流回路（131）的一部分。

公开(公告)号：US20110048773A1

公开(公告)日：2011-03-03

申请号：US12840696

申请日：2010-07-21

Applicant: Masahiro Kaneko ,  Satoru Kose ,  Hirokazu Higashi

Inventor： Masahiro Kaneko ,  Satoru Kose ,  Hirokazu Higashi

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/10

CPC classification number: H05K3/42 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/115 ,  H05K3/007 ,  H05K3/108 ,  H05K3/22 ,  H05K3/388 ,  H05K2201/0344 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/1377 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole for a via conductor, a conductive circuit formed on one surface of the interlayer resin insulation layer, a via conductor formed in the penetrating hole and having a protruding portion protruding from the other surface of the interlayer resin insulation layer, and a surface-treatment coating formed on the surface of the protruding portion of the via conductor. The via conductor is connected to the conductive circuit and has a first conductive layer formed on the side wall of the penetrating hole and a plated layer filling the penetrating hole.

Abstract translation: 印刷电路板包括：具有用于通路导体的贯通孔的层间树脂绝缘层，形成在层间树脂绝缘层的一个表面上的导电电路;形成在该贯通孔中的通孔导体，并且具有从另一个突出的突出部 层间树脂绝缘层的表面和形成在通孔导体的突出部分的表面上的表面处理涂层。 通孔导体连接到导电电路，并且具有形成在穿透孔的侧壁上的第一导电层和填充穿透孔的镀层。

公开(公告)号：US07765692B2

公开(公告)日：2010-08-03

申请号：US12237955

申请日：2008-09-25

Applicant: Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

Inventor： Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

IPC: H01K3/10 ,  B28B19/00

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/116 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09381 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2203/0554 ,  H05K2203/0571 ,  H05K2203/107 ,  H05K2203/175 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.

Abstract translation: 在具有导体电路（6）的绝缘板（7）的表面上印刷包括热固性树脂的阻焊剂。 然后将阻焊剂热固化以形成具有低热膨胀系数的绝缘膜（1）。 然后将激光束（2）施加到要形成开口的绝缘膜的部分，以烧掉用于形成开口（10）的相同部分，由此导体电路（6）暴露。 该开口可以通过在其内表面上形成金属电镀膜而形成为导电孔。 优选地，形成外部连接垫以覆盖开口。 通过使用在电镀完成后优选用激光束切断的电镀铅来形成金属涂膜。