公开(公告)号：US20100270644A1

公开(公告)日：2010-10-28

申请号：US12763412

申请日：2010-04-20

Applicant: Lynne E. Dellis ,  Karl Hartmann Dietz ,  David Ross McGregor

Inventor： Lynne E. Dellis ,  Karl Hartmann Dietz ,  David Ross McGregor

IPC: H01L27/08 ,  H01L21/50

CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H05K3/025 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/083 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09718 ,  H05K2201/10674 ,  H05K2203/104

Abstract: Disclosed are methods of making a semiconductor package comprising at least one thin-film capacitor embedded into at least one build-up layer of said semiconductor package. A thin-film capacitor is provided wherein the thin-film capacitor has a first electrode and a second electrode separated by a dielectric. A temporary carrier layer is applied to the first electrode and the second electrode is patterned. A PWB core and a build-up material are provided, and the build-up material is placed between the PWB core and the patterned second electrode of said thin-film capacitor. The patterned electrode side of the thin-film capacitor is laminated to the PWB core by way of the build-up material, the temporary carrier layer is removed, and the first electrode is patterned.

Abstract translation: 公开了制造半导体封装的方法，该半导体封装包括嵌入到所述半导体封装的至少一个堆积层中的至少一个薄膜电容器。 提供了一种薄膜电容器，其中薄膜电容器具有由电介质隔开的第一电极和第二电极。 临时载体层被施加到第一电极并且第二电极被图案化。 提供PWB芯和堆积材料，并且积聚材料被放置在PWB芯和所述薄膜电容器的图案化的第二电极之间。 薄膜电容器的图案化电极侧通过积聚材料层叠到PWB芯上，去除临时载体层，并对第一电极进行图案化。

公开(公告)号：US07808769B2

公开(公告)日：2010-10-05

申请号：US11637709

申请日：2006-12-13

Applicant: Tomohiko Katoh ,  Kenji Horino ,  Yuko Saya

Inventor： Tomohiko Katoh ,  Kenji Horino ,  Yuko Saya

IPC: H01G4/008

CPC classification number: H01G4/33 ,  H01G4/008 ,  H01L27/016 ,  H05K1/162 ,  H05K3/38 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/2063 ,  H05K2203/1105 ,  Y10T29/49126 ,  Y10T29/49163 ,  Y10T29/49204 ,  Y10T29/49213

Abstract: A dielectric device has a first conductor and a dielectric disposed thereon. An intermediate region is formed between the first conductor and dielectric. In the intermediate region, an additive different from the first conductor and dielectric and the dielectric are mixed with each other. The additive contains at least one element of Si, Al, P, Mg, Mn, Y, V, Mo, Co, Nb, Fe, and Cr.

Abstract translation: 电介质器件具有设置在其上的第一导体和电介质。 在第一导体和电介质之间形成中间区域。 在中间区域中，与第一导体和电介质和电介质不同的添加剂彼此混合。 添加剂含有Si，Al，P，Mg，Mn，Y，V，Mo，Co，Nb，Fe和Cr中的至少一种元素。

公开(公告)号：US07795663B2

公开(公告)日：2010-09-14

申请号：US11157894

申请日：2005-06-21

Applicant: Seigi Suh ,  William J. Borland

Inventor： Seigi Suh ,  William J. Borland

IPC: H01L27/108 ,  H01L29/94

CPC classification number: H01L21/02197 ,  H01G4/1227 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/31691 ,  H01L28/55 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355

Abstract: The present invention is directed to a dielectric thin film composition comprising: (1) one or more barium/titanium-containing additives selected from (a) barium titanate, (b) any composition that can form barium titanate during firing, and (c) mixtures thereof; dissolved in (2) organic medium; and wherein said thin film composition is doped with 0.002-0.05 atom percent of a dopant comprising an element selected from Sc, Cr, Fe, Co, Ni, Ca, Zn, Al, Ga, Y, Nd, Sm, Eu, Gd, Dy, Ho, Er, Yb, Lu and mixtures thereof and to capacitors comprising such compositions.

Abstract translation: 本发明涉及一种电介质薄膜组合物，其包括：（1）一种或多种选自（a）钛酸钡的钡/钛的添加剂，（b）在烧制期间可形成钛酸钡的任何组合物，和（c） 其混合物; 溶于（2）有机介质; 并且其中所述薄膜组合物掺杂0.002-0.05原子％的包含选自Sc，Cr，Fe，Co，Ni，Ca，Zn，Al，Ga，Y，Nd，Sm，Eu，Gd中的元素的掺杂剂， Dy，Ho，Er，Yb，Lu及其混合物，以及包含这种组合物的电容器。

公开(公告)号：US20100200285A1

公开(公告)日：2010-08-12

申请号：US12763455

申请日：2010-04-20

Applicant: Takashi KARIYA ,  Hironori Tanaka

Inventor： Takashi KARIYA ,  Hironori Tanaka

IPC: H05K1/16 ,  C23C14/34 ,  H01G4/06 ,  H01G4/008

CPC classification number: H05K1/162 ,  H01L21/4867 ,  H01L23/498 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/388 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A method of producing a capacitor for a printed circuit board includes producing high-dielectric sheets and selecting ones of the high-dielectric sheets, which are substantially free from a defect after the heat process. Each of the high-dielectric sheets is produced by providing a first electrode, forming a first sputter film on the first electrode, forming an intermediate layer on the first sputter film by calcining a sol-gel film, forming a second sputter film on the intermediate layer, and providing a second electrode on the second sputter film. The high-dielectric sheets are subjected to a heat process in which the high-dielectric sheets are subjected to a first temperature at least once and a second temperature higher than the first temperature at least once.

Abstract translation: 一种印刷电路板用电容器的制造方法，其特征在于，制造高介电质片材，并选择在热处理后基本上不存在缺陷的高电介质片材。 每个高电介质片通过提供第一电极来制造，在第一电极上形成第一溅射膜，通过煅烧溶胶 - 凝胶膜在第一溅射膜上形成中间层，在中间层上形成第二溅射膜 并且在第二溅射膜上提供第二电极。 对高电介质片材进行热处理，其中高电介质片材经受至少一次的第一温度和比第一温度高至少一次的第二温度。

公开(公告)号：US07755166B2

公开(公告)日：2010-07-13

申请号：US12401127

申请日：2009-03-10

Applicant: Takashi Kariya

Inventor： Takashi Kariya

IPC: H01L29/00

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2203/0152 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not formed in the first thin-film small electrode 41aa, and a ground post 62a and a via hole 62b are not formed in the second thin-film small electrode 42aa, either. As a result, the short-circuited small electrodes 41aa and 42aa are electrically connected to neither a power supply line nor a ground line, and become a potential independent from a power supply potential and a ground potential. Therefore, in the thin-film capacitor 40, only the portion where the short-circuited small electrodes 41aa and 42aa sandwich the high dielectric layer 43 loses the capacitor function, and portions where other thin-film small electrodes 41a and 42a sandwich the high dielectric layer 43 maintain the capacitor function.

公开(公告)号：US07736397B2

公开(公告)日：2010-06-15

申请号：US11730979

申请日：2007-04-05

Applicant: Seung Eun Lee ,  Yul Kyo Chung ,  Hyung Dong Kang ,  Hyun Ju Jin

Inventor： Seung Eun Lee ,  Yul Kyo Chung ,  Hyung Dong Kang ,  Hyun Ju Jin

IPC: H01L21/8242 ,  H01G9/00

CPC classification number: H04R19/00 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0346 ,  H05K2203/0353 ,  Y10T29/417 ,  Y10T29/42 ,  Y10T29/43 ,  Y10T29/435

Abstract: A method for manufacturing a capacitor embedded in a PCB includes: preparing a copper clad lamination (CCL) substrate having a reinforcement member and copper foils formed on both surfaces of the reinforcement member; planarizing surfaces of the copper foils of the CCL substrate; forming a dielectric layer on the planarized surface of the copper foils; and forming a top electrode on the dielectric layer.

Abstract translation: 一种嵌入在PCB中的电容器的制造方法，其特征在于，包括：具有加强部件的铜包层压（CCL）基板和形成在所述加强部件的两面上的铜箔; 平坦化CCL基板的铜箔表面; 在铜箔的平坦化表面上形成电介质层; 并在电介质层上形成顶部电极。

公开(公告)号：US20100143681A1

公开(公告)日：2010-06-10

申请号：US12531845

申请日：2008-03-27

Applicant: Hiroyuki Yano ,  Masaya Nogi ,  Kentarou Abe ,  Shinsuke Ifuku ,  Takashi Kurihara

Inventor： Hiroyuki Yano ,  Masaya Nogi ,  Kentarou Abe ,  Shinsuke Ifuku ,  Takashi Kurihara

IPC: B32B17/06

CPC classification number: B32B27/38 ,  B32B17/067 ,  B32B27/06 ,  B32B27/20 ,  B32B27/308 ,  B32B2262/062 ,  B32B2307/54 ,  B32B2307/702 ,  B32B2307/7242 ,  B32B2457/00 ,  H05K1/0393 ,  H05K2201/0175 ,  H05K2201/0284 ,  Y10T428/24975

Abstract: A flexible substrate 1 of the present invention is formed of a thin glass sheet 10 having a thickness of 50 μm or less and a composite material sheet 20 having a thickness of 100 μm or less which are laminated together, the composite material sheet 20 being formed of a composite material of an aggregation of cellulose nanofiber and amorphous synthetic resin.

Abstract translation: 本发明的柔性基板1由厚度为50μm以下的薄玻璃板10和层叠在一起的厚度为100μm以下的复合材料片20形成，复合材料片20形成 的纤维素纳米纤维和无定形合成树脂的聚集体的复合材料。

公开(公告)号：US20100112372A1

公开(公告)日：2010-05-06

申请号：US12596880

申请日：2008-04-17

Applicant: Claus Peter Kluge

Inventor： Claus Peter Kluge

IPC: B32B3/30 ,  B32B18/00 ,  B32B15/04 ,  B32B3/26 ,  B32B5/18 ,  B32B3/00 ,  C25D7/00 ,  B32B5/00 ,  C04B37/02

CPC classification number: C04B37/02 ,  C04B37/021 ,  C04B37/026 ,  C04B2237/121 ,  C04B2237/122 ,  C04B2237/123 ,  C04B2237/124 ,  C04B2237/125 ,  C04B2237/34 ,  C04B2237/343 ,  C04B2237/348 ,  C04B2237/365 ,  C04B2237/366 ,  C04B2237/368 ,  H01L23/15 ,  H01L23/3731 ,  H01L23/49822 ,  H01L23/49883 ,  H01L23/49894 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0203 ,  H05K1/0254 ,  H05K1/0284 ,  H05K1/0306 ,  H05K3/245 ,  H05K2201/0175 ,  H05K2201/09045 ,  Y10T428/12389 ,  Y10T428/12479 ,  Y10T428/12576 ,  Y10T428/12618 ,  Y10T428/24355 ,  Y10T428/249953 ,  Y10T428/26 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A component having a ceramic base the surface of which is covered in at least one area by a metalized coating, the ceramic base being spatially structured and the partial discharge resistance between at least two layers of a metalized structure produced from the same or different materials and between the layer of a metalized structure and the ceramic being

Abstract translation: 一种具有陶瓷基体的部件，其表面通过金属化涂层在至少一个区域中被覆盖，陶瓷基体是空间结构的，并且由相同或不同材料制成的至少两层金属化结构之间的部分放电电阻和 在金属化结构层和陶瓷之间<20pC。

公开(公告)号：US07649748B2

公开(公告)日：2010-01-19

申请号：US11917085

申请日：2006-06-14

Applicant: Takashi Kariya ,  Hironori Tanaka

Inventor： Takashi Kariya ,  Hironori Tanaka

IPC: H05K7/00

CPC classification number: H05K1/18 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4652 ,  H05K7/00 ,  H05K2201/0175 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/49133 ,  Y10T29/49162 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A multilayer printed wiring board includes a mounting portion supporting a semiconductor device and a layered capacitor portion including first and second layered electrodes and a ceramic high-dielectric layer therebetween. The first layered electrode is connected to a ground line and the second layered electrode is connected to a power supply line. The ratio of number of via holes, each constituting a conducting path part electrically connecting a ground pad to the ground line of a wiring pattern and passing through the second layered electrode in non-contact, to number of ground pads is 0.05 to 0.7. The ratio of number of second rod-shaped conductors, each constituting a conducting path part electrically connecting a power supply pad to the power supply line of the wiring pattern and passing through the first layered electrode in non-contact, to number of power supply pad is 0.05 to 0.7.

Abstract translation: 多层印刷布线板包括支撑半导体器件的安装部分和包括第一和第二层状电极的层状电容器部分和其间的陶瓷高介电层。 第一层状电极连接到地线，第二层状电极连接到电源线。 构成将接地焊盘与布线图案的接地线电连接并且非接触地穿过第二层状电极的导电路径部分的通孔数量的比率与接地焊盘数目的比为0.05〜0.7。 第二棒状导体的数量比构成将电源焊盘与布线图案的电源线电连接并且非接触地穿过第一层状电极的导电路径部分的数量与供电焊盘的数量 为0.05〜0.7。

公开(公告)号：US20090242257A1

公开(公告)日：2009-10-01

申请号：US12410699

申请日：2009-03-25

Applicant: Shinichiro KAKEI ,  Kenji HORINO ,  Hitoshi SAITA ,  Yasunobu OIKAWA

Inventor： Shinichiro KAKEI ,  Kenji HORINO ,  Hitoshi SAITA ,  Yasunobu OIKAWA

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K3/382 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2203/033

Abstract: In a dielectric element, the side faces are roughened so that the surface roughness Ra is 15 nm or greater. By this means, the area of contact between a glass epoxy resin substrate and insulating material is increased, adhesion with resin substrates is improved, and strength and reliability can be enhanced when buried between two resin substrates. In the dielectric element, the surface roughness Ra of side surfaces is 5000 nm or less, so that when burying the dielectric element between a glass epoxy resin substrate and insulating material, the occurrence of air bubbles between the surface of the dielectric element and the resin can be prevented.

Abstract translation: 在电介质元件中，侧面粗糙化，使得表面粗糙度Ra为15nm以上。 通过这种方式，玻璃环氧树脂基板和绝缘材料之间的接触面积增加，与树脂基板的粘合性提高，并且当埋在两个树脂基板之间时可以提高强度和可靠性。 在电介质元件中，侧面的表面粗糙度Ra为5000nm以下，因此当在玻璃环氧树脂基板和绝缘材料之间埋入电介质元件时，介电元件表面与树脂之间产生气泡 可以防止。