公开(公告)号：US20030018940A1

公开(公告)日：2003-01-23

申请号：US09911634

申请日：2001-07-23

Inventor： James A. McCall ,  Michael W. Leddige

IPC: H03M013/00

CPC classification number: H05K1/0246 ,  G11C5/063 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10022

Abstract: In some embodiments, the invention includes a system having first, second, third and fourth modules; and a circuit board including first, second, third, and fourth module connectors to receive the first and second modules, respectively. The system includes among other things a first group of paths of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector, to the second module, back to the second module connector, to terminations, wherein the first group of paths include a first short loop through section in the first module and a second short loop through section in the second module, to each couple to stubs for corresponding first and second chips of the first and second modules.

Abstract translation: 在一些实施例中，本发明包括具有第一，第二，第三和第四模块的系统; 以及电路板，包括分别接收第一和第二模块的第一，第二，第三和第四模块连接器。 该系统包括第一组导体，从电路板延伸到第一模块连接器，第一组件，第一模块连接器，电路板，第二模块连接器，第二组件连接器 模块，返回到第二模块连接器，到终端，其中第一组路径包括第一模块中的第一短循环部分和第二模块中的第二短循环部分，每个耦合到短截线用于对应的第一和 第一和第二模块的第二芯片。

公开(公告)号：US20020167331A1

公开(公告)日：2002-11-14

申请号：US09967746

申请日：2001-09-28

Applicant: Via Technologies, Inc

Inventor： Jin-Cheng Huang ,  Ching Fu Chuang

IPC: H03K019/003

CPC classification number: H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H05K1/0246 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2201/10522 ,  H05K2201/10689

Abstract: A bus architecture for the application of data transmission between distinct integrated circuits. The bus architecture includes at least one transmission line connecting with I/O pin of ICs for transmitting data. In a middle point of the transmission line, there is a middle resistor with a resistance value preferably equal to the characteristic impedance of the transmission line. In addition, there are internal pull-up resistors within the ICs, which has a first end coupled to the I/O pin and a second end coupled to the voltage source. Each pull-up resistor has a resistance value higher than the characteristic impedance of the transmission line, for example, 2 or 3 times of the characteristic impedance, for suppressing the rising edge ringback.

Abstract translation: 用于在不同集成电路之间应用数据传输的总线架构。 总线架构包括至少一条与IC的I / O引脚连接的传输线，用于发送数据。 在传输线的中点处，存在电阻值优选等于传输线的特性阻抗的中间电阻。 此外，IC内部有上拉电阻，其具有耦合到I / O引脚的第一端和耦合到电压源的第二端。 每个上拉电阻具有比传输线的特性阻抗高的电阻值，例如特性阻抗的2或3倍，用于抑制上升沿回波。

公开(公告)号：US06452442B1

公开(公告)日：2002-09-17

申请号：US08567379

申请日：1995-12-04

Applicant: David P. Laude

Inventor： David P. Laude

IPC: H03B100

CPC classification number: H03K17/161 ,  H03F3/193 ,  H03K19/01721 ,  H05K1/023 ,  H05K1/0231 ,  H05K2201/09254 ,  H05K2201/10022 ,  H05K2201/10689

Abstract: A noise immunity circuit has a distributed electrical plane to which noise susceptible components are coupled. Also, in a close proximity are noise generating circuits that generate electrical noise onto the distributed electrical plane that affect the noise susceptible components. A coupling means is used to couple the noise susceptible circuits to the distributed electrical plane so that the noise of the distributed electrical plane is common to all points in the noise susceptible circuit. Also, inputs and power to the circuit are coupled to the distributed electrical plane so that the common noise is imposed upon them. Coupling preferably takes place through a variety of capacitors and resistors so that high frequency noise is coupled to the noise susceptible circuit.

Abstract translation: 噪声抗扰电路具有耦合噪声敏感元件的分布式电平面。 而且，靠近的是产生电噪声到分布式电平面上的噪声产生电路，这些噪声产生电路影响噪声易受影响的部件。 耦合装置用于将噪声敏感电路耦合到分布式电平面，使得分布式电平面的噪声对于噪声敏感电路中的所有点是共同的。 此外，电路的输入和功率被耦合到分布式电平面，使得对它们施加公共噪声。 耦合优选通过各种电容器和电阻器进行，使得高频噪声耦合到噪声敏感电路。

公开(公告)号：US06407345B1

公开(公告)日：2002-06-18

申请号：US09700592

申请日：2000-11-17

Applicant: Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

Inventor： Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

IPC: H01R909

CPC classification number: H01R9/09 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/0256 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/184 ,  H05K3/241 ,  H05K3/382 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/0594 ,  Y10T29/49155 ,  Y10T29/49194 ,  Y10T428/31504

Abstract: A filet F is added to a portion constituting a corner portion C equal to or smaller than 90° in a crossing portion X of wiring patterns 58b, 58c and 58d, and a wiring pattern 58 is formed. Since the filet F is added, the wiring patterns are not made thin and are not disconnected in the crossing portion X. Further, since there is no stress concentrated to the crossing portion X, disconnection is not caused in the wiring patterns and no air bubbles are left between the crossing portion X of the wiring patterns and an interlayer resin insulating layer so that reliability of a printed wiring board is improved.

Abstract translation: 在布线图案58b，58c和58d的交叉部分X中，在构成拐角部分C等于或小于90°的部分上添加一个纸条F，并形成布线图案58。 由于添加了纸张F，所以布线图案不会变薄，并且在交叉部分X中不会断开。另外，由于不会对交叉部分X集中的应力，因此布线图案中不会导致断线，也不会产生气泡 留在布线图案的交叉部分X和层间树脂绝缘层之间，从而提高了印刷线路板的可靠性。

公开(公告)号：US06333472B1

公开(公告)日：2001-12-25

申请号：US09673108

申请日：2000-12-04

Applicant: Richard Weatherley

Inventor： Richard Weatherley

IPC: H01R1204

CPC classification number: H05K1/0228 ,  H01R13/6461 ,  H01R13/7195 ,  H05K2201/09254 ,  H05K2201/09672 ,  H05K2201/10189

Abstract: A circuit board (1) for use in a connector between cables of a data transmission system has at least one array of input terminals (T1-T8) for incoming signals, at least one array of output terminals (t1-t8) for outgoing signals, and a respective conductive track (5) connecting each input terminal to a respective output terminal. Closed loops (6, 7, 8) of conductive material are connected to at least some of the terminals or conductive tracks, the loops being positioned on the circuit board to reduce crosstalk from the levels which would exist within the connector in the absence of such closed loops. The loops associated with one terminal will be positioned on the board opposite loops associated with another terminal or terminals to produce coupling therebetween. The invention is particularly applicable to RJ45 plug and jack systems.

Abstract translation: 用于数据传输系统的电缆之间的连接器的电路板（1）具有用于输入信号的至少一个输入端子阵列（T1-T8），用于输出信号的至少一个输出端子阵列（t1-t8） 以及将每个输入端子连接到相应的输出端子的相应导电轨道（5）。 导电材料的闭环（6,7,8）连接到至少一些端子或导电轨道，环路定位在电路板上，以便在不存在这种情况的情况下减小连接器内存在的电平的串扰 闭环。 与一个终端相关联的环路将被定位在板上与另一终端相关联的环路上，以在它们之间产生耦合。 本发明特别适用于RJ45插头和插孔系统。

公开(公告)号：US5964854A

公开(公告)日：1999-10-12

申请号：US913277

申请日：1997-08-27

Applicant: Herman Roozenbeek ,  Bernd Tepass

Inventor： Herman Roozenbeek ,  Bernd Tepass

IPC: H05K9/00 ,  H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  G06I13/00 ,  H02B1/00 ,  H05K5/00

CPC classification number: H05K1/0216 ,  H05K1/181 ,  H05K1/0231 ,  H05K1/0298 ,  H05K2201/09254 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09972 ,  H05K2201/10015 ,  H05K2201/10166 ,  H05K2201/10689 ,  Y02P70/611

Abstract: In the case of a card cage for an electronic control unit having signal-processing analog and/or digital components, high-speed digital components, as well as components having both signal-processing functional parts, as well as high-speed digital functional parts and power components, which are arranged on a multilayer printed-circuit board and are electroconductively connected to a shared ground plane, the signal-processing components of each module having a shared connection to the common ground plane, the radiated interference from the control unit produced by high-frequency interference currents can be reduced, and high current densities in the ground plane and resultant potential shifts can be prevented from adversely affecting the signal processing, in that the signal-processing components are combined into signal-processing modules having at least one shared function, and the ground connections of all components of such a functional module are routed in each case via conductor connections to a common point of connection conductively connected over the shortest path to the shared ground plane, and the high-speed digital and power components are directly linked to the shared ground plane. By introducing an additional voltage-supply plane, the radiated interference from the control unit is able to be further reduced.

Abstract translation: PCT No.PCT / DE96 / 01334 Sec。 371日期1997年8月27日第 102（e）日期1997年8月27日PCT提交1996年7月20日PCT公布。 公开号WO97 / 13395 日期1997年4月10日在具有信号处理模拟和/或数字组件的电子控制单元的卡笼的情况下，高速数字组件以及具有信号处理功能部件的组件以及高 布置在多层印刷电路板上并且与电力共同接地平面连接的数字功能部件和功率部件，每个模块的信号处理部件具有与公共接地层的共用连接，辐射干扰 可以降低由高频干扰电流产生的控制单元，并且可以防止接地层中的高电流密度和合成的电位移动对信号处理产生不利影响，因为信号处理组件被组合成信号处理 具有至少一个共享功能的模块，并且这些功能模块的所有组件的接地连接在每个c中被路由 通过导体连接到通过最短路径传导连接到共用接地层的公共连接点，高速数字和功率部件直接连接到共享接地层。 通过引入附加的电压供应平面，可以进一步减少来自控制单元的辐射干扰。

公开(公告)号：US5717556A

公开(公告)日：1998-02-10

申请号：US638939

申请日：1996-04-25

Applicant: Keiichirou Yanagida

Inventor： Keiichirou Yanagida

IPC: H05K1/18 ,  H05K1/00 ,  H05K1/02 ,  H05K1/14 ,  H05K3/00 ,  H05K1/11 ,  H01R9/09

CPC classification number: H05K3/4691 ,  H05K1/0278 ,  H05K1/028 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09254 ,  H05K2201/0979 ,  H05K3/0058

Abstract: In a printed-wiring board, first and second hard substrates each having electronic components mounted thereon are connected through a flexible substrate interposed therebetween. A circuit pattern printed on each of the hard and flexible substrates electrically connects the electronic components mounted on the hard substrates through the flexible substrate. The circuit pattern includes a plurality of parallel-connected signal lines. The parallel-connected signal lines are spatially separated on the flexible substrate, and the both ends of the parallel-connected signal lines are located in the hard substrates, respectively. A single signal line of the circuit pattern branches on one hard substrate into the parallel-connected signal lines, which extend through the flexible substrate and are converged to a single signal line on the other hard substrate.

Abstract translation: 在印刷电路板中，安装有电子部件的第一和第二硬质基板通过插入其间的柔性基板连接。 印刷在每个硬质和柔性基板上的电路图案通过柔性基板电连接安装在硬质基板上的电子部件。 电路图案包括多个并联连接的信号线。 并联连接的信号线在柔性基板上空间分离，并联连接的信号线的两端分别位于硬质基板上。 电路图案的单个信号线在一个硬质基板上分支成并联连接的信号线，其延伸穿过柔性基板并且会聚到另一个硬质基板上的单个信号线。

公开(公告)号：US4947144A

公开(公告)日：1990-08-07

申请号：US347449

申请日：1989-05-04

Applicant: Yves Le Nohaic

Inventor： Yves Le Nohaic

IPC: G06F3/00 ,  G06F13/40 ,  H01P5/00 ,  H01P5/02 ,  H01P5/12 ,  H03K19/0175 ,  H05K1/02

CPC classification number: H01P5/12 ,  H05K1/025 ,  H05K1/023 ,  H05K1/0246 ,  H05K2201/09254 ,  H05K2201/09727

Abstract: The device of the invention comprises a bus (B) constituted by a series of lengths each of constant width and each of arbitrary length. The widths of the different lengths vary along the bus from one length to another, with the length connected to an emitter (E) being the widest. Each junction between two lengths is connected by a branch line (L2 to Ln) to an electronic circuit (D2 to Dn). The lines are of arbitrary lengths and have the same characteristic impedance. The end length (B1) of the bus is connected to an electronic circuit (D1). The end length and the branch lines are all terminated on their characteristic impedance. When signals are distributed symmetrically, distribution takes place from a differential emitter via two identical buses which are connected via differential lines to the electronic circuits.

Abstract translation: 本发明的装置包括由具有恒定宽度和每个任意长度的一系列长度构成的总线（B）。 不同长度的宽度沿着总线从一个长度变化到另一个长度，其长度连接到发射器（E）最宽。 两个长度之间的每个连接点通过分支线路（L2至Ln）连接到电子电路（D2至Dn）。 这些线具有任意长度并且具有相同的特性阻抗。 总线的端长（B1）连接到电子电路（D1）。 端长和分支线全部以其特征阻抗端接。 当信号对称分布时，通过经由差分线路连接到电子电路的两条相同的总线从差分发射器进行分配。

公开(公告)号：US20240260172A1

公开(公告)日：2024-08-01

申请号：US18040029

申请日：2022-09-08

Applicant: HONOR DEVICE CO., LTD.

Inventor： Puwei BAI ,  Haojie LI

IPC: H05K1/02

CPC classification number: H05K1/0245 ,  H05K1/0225 ,  H05K2201/09254 ,  H05K2201/093 ,  H05K2201/10098 ,  H05K2201/10121

Abstract: A circuit board and an electronic device is provided. The circuit board includes: a signal layer, where the signal layer includes at least one set of differential wires, and the at least one set of differential wires includes a first differential wire and a second differential wire that are insulated from each other; the first differential wire includes a first part, a second part, and a third part that are arranged successively in an extension direction of the first differential wire; and the second differential wire includes a fourth part, a fifth part, and a sixth part that are arranged successively in an extension direction of the second differential wire; and a ground plane, where the ground plane is disposed on at least one side of the signal layer, and is insulated from the signal layer; and the ground plane is provided with a first hollowed-out portion.

公开(公告)号：US20230262881A1

公开(公告)日：2023-08-17

申请号：US17672974

申请日：2022-02-16

Applicant: Nanning FuLian FuGui Precision Industrial Co., Ltd.

Inventor： YU-CHIH CHUEH

IPC: H05K1/02 ,  H01R12/70

CPC classification number: H05K1/0251 ,  H01R12/7082 ,  H05K2201/09254

Abstract: A branch coupler includes a first branch, comprising an input end, an isolation end, a first transmission line, a first branch line and a second branch line, the input end is electrically connected to the isolation end through the first transmission line, the first branch line is electrically connected to input end, and second branch line is electrically connected to the isolation end; a second branch, comprising a first output end, a second output end, a second transmission line, a third branch line and a fourth branch line, the first output end and the second output end are connected through second transmission line, the third branch line is connected to the first output end, and the fourth branch line is connected to the second output end; the first branch line is connected to the third branch line, and the second branch line is connected to the fourth branch line.