公开(公告)号：US07614141B2

公开(公告)日：2009-11-10

申请号：US11355713

申请日：2006-02-16

Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Roger D. Weekly

Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Colm B. O'Reilly ,  Roger D. Weekly

IPC: H01K3/10

CPC classification number: H05K1/162 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09609 ,  H05K2201/09627 ,  Y10T29/49117 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.

Abstract translation: 提供了一种用于多层陶瓷（MLC）衬底的低电感通孔布置。 通过MLC衬底和示例性实施例的通孔布置，给定接触焊盘阵列的通孔电感减小。 这种减少是通过引入T-jogs和附加通孔来实现的。 这些T形点动和附加通孔形成额外的电流路径，从而产生额外的并联电感，从而减小通路电感。 在一个说明性实施例中，附加的T形点动和通孔被添加到接触焊盘阵列的中心部分。 T-jogs由MLC的布线层中的两个点动组成，每个点动都朝向与接触垫阵列中的相邻接触焊盘相关联的通孔。 这些额外的T形点动和通孔形成与现有循环平行的额外的电流回路，从而减小通孔的总电感。

公开(公告)号：US20090236141A1

公开(公告)日：2009-09-24

申请号：US12285133

申请日：2008-09-29

Applicant: Han Kim ,  Mi-Ja Han ,  Hyo-Jic Jung

Inventor： Han Kim ,  Mi-Ja Han ,  Hyo-Jic Jung

IPC: H05K1/02

CPC classification number: H01P1/2005 ,  H01L2224/16 ,  H01P1/203 ,  H05K1/0236 ,  H05K1/0237 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09663 ,  H05K2201/09681

Abstract: According to an embodiment of the present invention, an electromagnetic bandgap structure can include: at least three conductive plates; a first stitching via, configured to electrically connect any one of the conductive plates to another conductive plate; and a second stitching via, configured to electrically connect the one conductive plate to yet another conductive plate. In the electromagnetic bandgap structure of the present invetion, the first stitching via can electrically connect the one conductive plate to another conductive plate by allowing a part of the first stitching via to be connected through a planar surface above the one conductive plate, and the second stitching via can electrically connect the one conductive plate to yet another conductive plate by allowing a part of the second stitching via to be connected through a planar surface below the one conductive plate.

Abstract translation: 根据本发明的实施例，电磁带隙结构可以包括：至少三个导电板; 第一缝合通孔，被配置为将任一导电板电连接到另一个导电板; 以及第二缝合通孔，其被配置为将所述一个导电板电连接到另一个导电板。 在本发明的电磁带隙结构中，第一缝合通孔可以通过允许第一缝合通孔的一部分通过一个导电板上的平面连接而将一个导电板电连接到另一个导电板， 缝合通孔可以通过允许第二缝合通孔的一部分通过一个导电板下面的平坦表面连接而将一个导电板电连接到另一个导电板。

公开(公告)号：US20090179305A1

公开(公告)日：2009-07-16

申请号：US12343740

申请日：2008-12-24

Applicant: Yoshiaki Shimizu

Inventor： Yoshiaki Shimizu

IPC: H01L21/768 ,  H01L23/538

CPC classification number: H05K3/242 ,  H01L2224/11 ,  H05K1/114 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/429 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/10734 ,  H05K2203/0242 ,  H05K2203/175

Abstract: According to the present invention, on a double-sided substrate 1, a plurality of through-holes 2 connected to one wire 6 for plating as well as wiring are collectively arranged within a narrow range close to the connection portion. After a plating process, a penetrating hole 12 is formed and the connection potion is cut off. Thus, the wire 6 for plating and the collectively arranged through-holes 2 are made independent of one another so that no electric conduction occurs among the wire 6 for plating and the through-holes 2.

Abstract translation: 根据本发明，在双面基板1上，与连接部分附近的窄范围内共同配置多个与电镀用布线6连接的通孔2以及配线。 电镀处理后，形成贯通孔12，切断连接部。 因此，用于电镀的导线6和共同设置的通孔2彼此独立，使得在用于电镀的导线6和通孔2之间不​​会发生导电。

公开(公告)号：US07554040B2

公开(公告)日：2009-06-30

申请号：US11460943

申请日：2006-07-28

Applicant: Yoshitada Nakao ,  Masateru Tsutsumi ,  Takayuki Fujikawa

Inventor： Yoshitada Nakao ,  Masateru Tsutsumi ,  Takayuki Fujikawa

IPC: H05K1/16

CPC classification number: H05K1/116 ,  B23K1/085 ,  H05K3/3447 ,  H05K3/3468 ,  H05K3/3494 ,  H05K3/429 ,  H05K2201/09618 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2201/09809 ,  H05K2203/0557 ,  H05K2203/304 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A printed circuit board suitable for dip soldering of component leads in through holes using lead free solder. The printed circuit board includes a plurality of via holes arranged around each through hole in which a component lead is inserted, whereby solder wicking up into the through hole is enhanced and air entrapment is prevented during the dip soldering operation, and heat fatigue resistance of solder joints is improved.

Abstract translation: 适用于使用无铅焊料将元件引线浸入通孔的印刷电路板。 印刷电路板包括布置在每个通孔周围的多个通孔，其中插入有部件引线，从而增加了浸入通孔中的焊料，并且在浸焊操作期间防止了空气滞留，并且焊料的耐热疲劳性 关节得到改善。

公开(公告)号：US07528616B2

公开(公告)日：2009-05-05

申请号：US11140455

申请日：2005-05-27

Applicant: Carlo Grilletto ,  Zafer S. Kutlu

Inventor： Carlo Grilletto ,  Zafer S. Kutlu

IPC: G01R31/02

CPC classification number: G01R31/043 ,  G01R1/0433 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/09627 ,  H05K2201/10325 ,  H05K2201/10734 ,  H05K2203/162

Abstract: A zero automated electrical testing (ATE) interposer daughter card (IDC) is provided for use in a test apparatus for ATE. Embodiments of the IDC include a first side having a first set of pads for mounting I/O's of a test package; and a second side having a second set of pads coupled to the first set of pads for replicating the first set of pads, wherein the second set of pads is located in area of the interposer card horizontally offset from the first set of pads, such that ATE measurements are obtained by removably inserting only a portion of the interposer card containing the second set of pads into an ATE test socket.

Abstract translation: 提供零自动电气测试（ATE）插入器子卡（IDC）用于ATE的测试装置。 IDC的实施例包括具有用于安装测试包的I / O的第一组垫的第一侧; 以及第二侧，其具有耦合到所述第一组焊盘的第二组焊盘，用于复制所述第一组焊盘，其中所述第二组焊盘位于所述插入器卡的与所述第一组焊盘水平偏移的区域中，使得 通过将仅包含第二组焊盘的插入卡的一部分可拆卸地插入到ATE测试插座中来获得ATE测量。

公开(公告)号：US20090071709A1

公开(公告)日：2009-03-19

申请号：US12076650

申请日：2008-03-20

Applicant: Mi-Ja Han ,  Han Kim ,  Ja-Bo Koo

Inventor： Mi-Ja Han ,  Han Kim ,  Ja-Bo Koo

IPC: H05K1/02

CPC classification number: H05K1/0236 ,  H05K2201/09309 ,  H05K2201/09627 ,  H05K2201/09663

Abstract: An electromagnetic bandgap structure and a printed circuit board that intercepts to transfer a signal having a predetermined frequency band are disclosed. In particularly, the electromagnetic bandgap structure includes a first metal layer and a second metal layer; a metal plate, placed between the first metal layer and a second metal layer; a multi-via, penetrating the first metal layer, passing through the same planar surface as an outer metal layer and turning toward the first metal layer to connect the metal plate and the first metal layer; and a dielectric layer, stacked in between the first metal layer and the metal plate, between the metal plate and the second metal layer and between the first metal layer and the outer metal layer. With the present invention, a bandgap frequency can be decreased without increasing the size of the metal plate.

Abstract translation: 公开了一种电磁带隙结构和用于传送具有预定频带的信号的印刷电路板。 特别地，电磁带隙结构包括第一金属层和第二金属层; 金属板，放置在第一金属层和第二金属层之间; 穿过第一金属层的多通孔，穿过与外部金属层相同的平面，并朝着第一金属层转动以连接金属板和第一金属层; 以及电介质层，层叠在所述第一金属层和所述金属板之间，所述金属板与所述第二金属层之间以及所述第一金属层与所述外部金属层之间。 通过本发明，可以在不增加金属板的尺寸的情况下降低带隙频率。

公开(公告)号：US07501839B2

公开(公告)日：2009-03-10

申请号：US11607973

申请日：2006-12-04

Applicant: Benson Chan ,  Frank D. Egitto ,  Voya R. Markovich

Inventor： Benson Chan ,  Frank D. Egitto ,  Voya R. Markovich

IPC: G01R31/02

CPC classification number: G01R1/06711 ,  G01R1/0735 ,  G01R1/07378 ,  H05K1/0393 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09627 ,  H05K2201/09745 ,  H05K2201/10378

Abstract: A test apparatus which uses a pair of substrates and housing to interconnect a host substrate (e.g., PCB) to an electronic device (e.g., semiconductor chip) to accomplish testing of the device. The apparatus includes a housing designed for being positioned on the PCB and have one of the substrates oriented therein during device engagement. The engaging contacts of the upper (second) substrate are sculpted to assure effective chip connection.

Abstract translation: 一种测试装置，其使用一对基板和壳体将主机基板（例如，PCB）与电子设备（例如，半导体芯片）相互连接，以实现设备的测试。 该装置包括被设计用于定位在PCB上的壳体，并且在装置接合期间其中一个基板定向于其中。 上（第二）衬底的接合触点被雕刻以确保有效的芯片连接。

公开(公告)号：US20090014865A1

公开(公告)日：2009-01-15

申请号：US12136316

申请日：2008-06-10

Applicant: Pao-Hung Chou ,  Chi-Liang Chu ,  Wei-Chun Wang

Inventor： Pao-Hung Chou ,  Chi-Liang Chu ,  Wei-Chun Wang

IPC: H01L23/34

CPC classification number: H05K1/0206 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/183 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09627 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A heat-conductive package structure includes a carrier board having a first surface and an opposing second surface and formed with a through opening passing the carrier board; a first heat-conductive structure including a heat-conductive hole in the through opening, a first heat-conductive sheet on the carrier board, and a second heat-conductive sheet on the carrier board, wherein the first and second heat-conductive sheets are conductively connected by the heat-conductive hole; a first dielectric layer formed on the first surface of the carrier board and formed with a first opening for exposing the first heat-conductive sheet; a second dielectric layer formed on the second surface of the carrier board and formed with at least a second opening for exposing a portion of the second heat-conductive sheet; and a second heat-conductive structure formed in the second opening and mounted on the second heat-conductive sheet.

Abstract translation: 导热封装结构包括具有第一表面和相对的第二表面的载体板，并形成有穿过承载板的通孔; 第一导热结构，其包括在通孔中的导热孔，载体板上的第一导热片和载体板上的第二导热片，其中第一和第二导热片是 由导热孔导电连接; 第一介电层，形成在所述载板的所述第一表面上，并形成有用于暴露所述第一导热片的第一开口; 第二电介质层，形成在所述载体板的第二表面上，并形成有用于暴露所述第二导热片的一部分的至少第二开口; 以及形成在第二开口中并安装在第二导热片上的第二导热结构。

公开(公告)号：US07478003B2

公开(公告)日：2009-01-13

申请号：US11175123

申请日：2005-07-05

Applicant: Peter C. Cowan ,  Markus F. Hirschbold

Inventor： Peter C. Cowan ,  Markus F. Hirschbold

IPC: G06F19/00

CPC classification number: H05K1/116 ,  G01R22/065 ,  H01R12/523 ,  H05K3/3447 ,  H05K3/3468 ,  H05K3/429 ,  H05K2201/09627 ,  H05K2201/09854

Abstract: A method and arrangement are disclosed for attaching one or more electrical bayonet-type blades to a circuit board with the bayonets being used to receive voltage and current signals from the electric circuit of an electrical meter. The arrangement includes a circuit board with at least one opening adapted to receive one blade. In addition, a sensor is coupled with the electric circuit to sense at least one electrical parameter from the circuit and generating a corresponding analog signal. A solder pad disposed on at least one surface of board surrounds the opening. Solder is applied around the electrically conducting bayonet on one surface of the circuit board and around the electrically conducting bayonet of the surface of the circuit board opposite to the solder pad.

Abstract translation: 公开了一种用于将一个或多个电刺刀型叶片附接到电路板的方法和装置，其中卡口用于从电表的电路接收电压和电流信号。 该装置包括具有至少一个适于接收一个叶片的开口的电路板。 此外，传感器与电路耦合以感测来自电路的至少一个电参数并产生对应的模拟信号。 设置在板的至少一个表面上的焊盘围绕开口。 在电路板的一个表面上以及与电路板的与焊盘相对的表面的导电卡口周围的电导卡口周围施加焊料。

公开(公告)号：US07449641B2

公开(公告)日：2008-11-11

申请号：US11492514

申请日：2006-07-24

Applicant: Yen-Hao Chen

Inventor： Yen-Hao Chen

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09627

Abstract: A high-speed signal transmission structure having parallel disposed and serially connected vias is disclosed. The structure is applicable to a multi-layered circuit board such as a high-speed digital circuit board for forming a high-speed signal transmission circuit on the high-speed digital circuit board. The structure includes a pair of parallel disposed and serially connected vias for connecting an upper conductive circuit installed on an upper layer of the multi-layered circuit board and a lower conductive circuit installed on a lower layer of the multi-layered circuit board. Compared with the prior art, an open stub formed by the remaining portion of the vias has become shorter, thereby reducing a resonance effect affecting the quality of signal transmission.