公开(公告)号：US20070134953A1

公开(公告)日：2007-06-14

申请号：US11298998

申请日：2005-12-09

Applicant: Francis Morana ,  Dennis Dupler ,  Charles Adams

Inventor： Francis Morana ,  Dennis Dupler ,  Charles Adams

IPC: H01R12/00

CPC classification number: H01R13/6477 ,  H01R13/6658 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/0253 ,  H05K1/117 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/10189 ,  Y10S439/941

Abstract: An electrical connector comprises a housing holding a circuit board. The circuit board has a top surface which includes a first region and a second region. Circuit traces are formed on the top surface and extend in the first and second regions. A first ground plane is disposed at a first depth in the circuit board below the circuit traces in the first region. The first depth is selected to provide a specific characteristic impedance of the circuit traces in the first region. A second ground plane is disposed at a second depth in the circuit board below the circuit traces in the second region. The second depth is selected to provide a specific characteristic impedance of the circuit traces in the second region.

Abstract translation: 电连接器包括容纳电路板的壳体。 电路板具有包括第一区域和第二区域的顶表面。 电路迹线形成在顶表面上并且在第一和第二区域中延伸。 第一接地平面设置在第一区域中的电路迹线下方的电路板中的第一深度处。 选择第一深度以在第一区域中提供电路迹线的特定阻抗。 第二接地平面设置在第二区域中的电路迹线下方的电路板中的第二深度处。 选择第二深度以在第二区域中提供电路迹线的特定阻抗。

公开(公告)号：US20070093107A1

公开(公告)日：2007-04-26

申请号：US11585959

申请日：2006-10-25

Applicant: Kenji Motohashi ,  Takashi Yanagimoto ,  Hideji Miyanishi ,  Kazumasa Aoki

Inventor： Kenji Motohashi ,  Takashi Yanagimoto ,  Hideji Miyanishi ,  Kazumasa Aoki

IPC: H01R29/00

CPC classification number: H05K1/117 ,  H05K1/0224 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/09727

Abstract: A design rule for a printed wiring board is provided. A conductive layer and a pad are separate from each other in a distance defined by the design rule, which sufficiently prevents the capacitance coupling between the conductive layer and the pad.

Abstract translation: 提供印刷电路板的设计规则。 导电层和焊盘在由设计规则限定的距离内彼此分开，这足以防止导电层和焊盘之间的电容耦合。

公开(公告)号：US20070090398A1

公开(公告)日：2007-04-26

申请号：US11583212

申请日：2006-10-18

Applicant: William McKinzie

Inventor： William McKinzie

IPC: H01L31/00

CPC classification number: H01P1/20 ,  H01P1/2005 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0236 ,  H05K1/0239 ,  H05K1/162 ,  H05K1/165 ,  H05K1/181 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09609 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A hybrid electromagnetic bandgap (EBG) structure for broadband suppression of noise on printed wiring boards includes an array of coplanar patches interconnected into a grid by series inductances, and a corresponding array of shunt LC networks connecting the coplanar patches to a second conductive plane. This combination of series inductances and shunt resonant vias lowers the cutoff frequency for the fundamental stopband. The series inductances and shunt capacitances may be implemented using surface mount component technology, or printed traces. Patches may also be interconnected by coplanar coupled transmission lines. The even and odd mode impedances of the coupled lines may be increased by forming slots in the second conductive plane disposed opposite to the transmission line, lowering the cutoff frequency and increasing the bandwidth of the fundamental stopband. Coplanar EBG structures may be integrated into power distribution networks of printed wiring boards for broadband suppression of electromagnetic noise.

Abstract translation: 用于宽带抑制印刷电路板上的噪声的混合电磁带隙（EBG）结构包括通过串联电感互连到电网中的共面贴片阵列，以及将共面贴片连接到第二导电平面的相应阵列的分流LC网络。 串联电感和并联谐振通孔的组合降低了基波阻带的截止频率。 串联电感和分流电容可以使用表面贴装元件技术或印刷迹线实现。 补片也可以通过共面耦合传输线相互连接。 可以通过在与传输线相对布置的第二导电平面中形成槽，降低截止频率并增加基带阻带的带宽来增加耦合线的偶模和奇模阻抗。 共面EBG结构可以集成到用于宽带抑制电磁噪声的印刷线路板的配电网络中。

公开(公告)号：US20070079276A1

公开(公告)日：2007-04-05

申请号：US11311655

申请日：2005-12-20

Applicant: Takayuki Ashida ,  Kenichirou Tsubone

Inventor： Takayuki Ashida ,  Kenichirou Tsubone

IPC: G06F17/50

CPC classification number: H05K3/0005 ,  G06F17/5081 ,  H05K1/0201 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/062 ,  H05K2201/0969

Abstract: A multilayered board data input unit inputs design data of a multilayered circuit board provided with through holes penetrating and mutually connecting solid-layer conductors disposed in a multilayer manner. A limitation rule setting unit sets a limitation rule for limiting the number of solid-layer conductors to be connected to the through holes. A separation processing unit separates connections of the solid-layer conductors to the through holes in the design data based on the limitation rule. At this time, when a solid-layer conductor to be separated from the through holes is selected as a candidate, the separation processing unit determines whether the solid-layer conductor is isolated by separation, when the solid-layer conductor is not isolated, determines isolation, and when the solid-layer conductor is isolated, stops separation.

Abstract translation: 多层板数据输入单元输入设置有穿透并相互连接以多层方式布置的固体层导体的通孔的多层电路板的设计数据。 限制规则设定单元设定用于限制要连接到通孔的固体导体的数量的限制规则。 分离处理单元基于限制规则将设计数据中的固体导体与通孔的连接分离。 此时，当选择与通孔分离的固体层导体作为候选时，分离处理单元通过分离确定固体层导体是否被隔离，当固体层导体未被隔离时，确定 隔离，当固体层导体隔离时，停止分离。

公开(公告)号：US20070034404A1

公开(公告)日：2007-02-15

申请号：US11341614

申请日：2006-01-30

Applicant: Na-Rae Shin ,  Dong-Han Kim

Inventor： Na-Rae Shin ,  Dong-Han Kim

IPC: H05K7/06

CPC classification number: H05K1/0271 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K1/118 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/09781 ,  H01L2924/00

Abstract: A TAB tape for a tape carrier package may have an opening formed in a shortest connection portion. The opening may be provided in the shortest connection portion and a portion of the corresponding second lead. The opening may be arranged near a boundary between the corresponding first lead and the shortest connection portion. The opening may be sized to reduce the change of the lead width from the first lead to the second lead.

Abstract translation: 用于载带封装的TAB带可以具有形成在最短连接部分中的开口。 开口可以设置在最短连接部分和相应的第二引线的一部分中。 开口可以布置在相应的第一引线和最短连接部分之间的边界附近。 该开口的尺寸可以减小引线宽度从第一引线到第二引线的变化。

公开(公告)号：US20070034403A1

公开(公告)日：2007-02-15

申请号：US11500510

申请日：2006-08-08

Applicant: Tsuyoshi Miura

Inventor： Tsuyoshi Miura

IPC: H05K1/18 ,  H01L23/498

CPC classification number: H05K3/3421 ,  H05K3/3468 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K2203/046 ,  Y02P70/613

Abstract: A four-way lead flat package IC-mount printed circuit board, carrying a four-way lead flat package IC and having front soldering land groups placed in front of the four way lead flat package IC and rear soldering land groups placed in the rear of the four-way lead flat package IC, has solder drawing lands, in a neighboring area, between the front soldering land groups and the rear soldering land groups adjacent to the front soldering land groups, and/or a trailing area of the rear soldering land groups. The solder drawing lands are formed with slits substantially parallel to the lines of soldering lands of the front soldering land groups or the rear soldering land groups placed in front of the solder drawing lands. These result in an advantageous effect of enabling the prevention of the occurrence of soldering bridges and soldering residues in the front soldering land groups or the rear soldering land groups.

Abstract translation: 一个四路铅扁平封装IC安装印刷电路板，载有四路铅扁平封装IC，并且前面的焊接区域放置在四通导线扁平封装IC的前面，后面的焊接焊盘组放置在 四路铅扁平封装IC，在相邻区域中，在前焊接区域组和与前焊接区域组相邻的后焊接区域之间具有焊接绘图区域和/或后焊接区域的后部区域 团体 焊料焊盘形成有大致平行于前焊接焊盘组的焊盘的焊缝的缝隙或者位于焊料焊盘前方的后焊接焊盘组。 这些产生的效果是能够防止前端焊接组或后焊接组中的焊接桥和焊料残留的发生。

公开(公告)号：US20070023202A1

公开(公告)日：2007-02-01

申请号：US11494744

申请日：2006-07-28

Applicant: Kiyoshi Shibata ,  Ryosuke Usui ,  Yasunori Inoue

Inventor： Kiyoshi Shibata ,  Ryosuke Usui ,  Yasunori Inoue

IPC: H05K1/00

CPC classification number: H05K3/445 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/44 ,  H05K2201/0382 ,  H05K2201/09054 ,  H05K2201/09609 ,  H05K2201/0969 ,  H05K2203/0323 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49165

Abstract: A circuit board and a circuit apparatus using the same which can prevent displacement and film exfoliation ascribable to thermal expansion, and suppress a drop in reliability at increasing temperatures. The circuit board of the circuit apparatus includes a metal substrate having pierced holes as a core member. Protrusions are formed on the top ends of the pierced holes, and depressions are formed in the bottom ends of the pierced holes. Wiring pattern layers are formed on both sides of this metal substrate via respective insulating layers. In order to establish electrical connection between the wiring pattern layers, a conductor layer which connects the wiring pattern layers is formed through the metal substrate via the pierced holes. The conductor layer thereby establishes electrical conduction between the wiring pattern layers. Furthermore, a semiconductor chip is directly connected to the surface side of the circuit board via solder balls.

Abstract translation: 一种电路板和使用该电路板的电路装置，其可以防止由于热膨胀而引起的位移和膜剥落，并且抑制在升高的温度下的可靠性降低。 电路装置的电路板包括具有穿孔作为芯构件的金属基板。 在穿孔的顶端形成突起，在穿孔的底端形成凹部。 接线图案层通过各自的绝缘层形成在该金属基板的两侧上。 为了建立布线图案层之间的电连接，通过穿孔穿过金属基板形成连接布线图案层的导体层。 导体层由此在布线图案层之间建立导电。 此外，半导体芯片通过焊球直接连接到电路板的表面侧。

公开(公告)号：US20060291678A1

公开(公告)日：2006-12-28

申请号：US11447864

申请日：2006-06-07

Applicant: Ryuji Awamura

Inventor： Ryuji Awamura

IPC: H04R25/00

CPC classification number: H05K3/303 ,  H04R1/06 ,  H05K1/0243 ,  H05K1/0269 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2203/166 ,  H05K2203/168 ,  Y02P70/613

Abstract: An electronic device which enables easily providing a mounting orientation recognition mark thereon while being provided with, on a end surface thereof, input/output terminals surrounded by a ground pattern. A substrate is provided within a case main body. A ground is formed on the surface of the substrate. An output terminal, a power terminal, a clock terminal, a GND terminal and a mounting orientation recognition mark hole have been formed on the ground through pattern removal. The main portion of the substrate is exposed through an opening in the case and the tip end portions of the output terminal and the like are slightly protruded from the end surface of the case main body. The ground pattern on the substrate, the case main body and the like are electrically connected to the GND terminal and the entire component is shielded.

公开(公告)号：US07152312B2

公开(公告)日：2006-12-26

申请号：US10073701

申请日：2002-02-11

Applicant: Gary Gottlieb

Inventor： Gary Gottlieb

IPC: H01R43/00 ,  H05K3/36

CPC classification number: H05K1/116 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for transmitting high-frequency current through a substrate is provided. The method comprises receiving the high-frequency current at a via passing through at least one conductive plane disposed within the substrate and coupled to the via with one or more tabs which span a gap between the at least one conductive plane and the via; and directing the high-frequency current along an uninterrupted path substantially on a surface of the via thereby bypassing the at least one conductive plane by conducting at least a portion of the high-frequency current between the one or more tabs.

Abstract translation: 提供了一种通过基板传输高频电流的方法。 该方法包括在穿过设置在衬底内的至少一个导电平面的通孔处接收高频电流，并且通过跨越至少一个导电平面和通孔之间的间隙的一个或多个接片连接到通孔; 以及基本上在所述通孔的表面上沿着不间断的路径引导所述高频电流，从而通过在所述一个或多个突片之间传导所述高频电流的至少一部分来绕过所述至少一个导电平面。

公开(公告)号：US20060274478A1

公开(公告)日：2006-12-07

申请号：US11147412

申请日：2005-06-06

Applicant: Macushla Chen ,  James Howard

Inventor： Macushla Chen ,  James Howard

IPC: H01G4/20 ,  H01G9/00

CPC classification number: H05K1/162 ,  H05K1/0216 ,  H05K1/165 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/1006

Abstract: An etched capacitor laminate for reducing electrical noise. The etched capacitor laminate is configured to be an element of a printed circuit board. The etched capacitor laminate comprises a first conductive sheet, an intermediate sheet of dielectric material, and a second conductive sheet. The first conductive sheet further comprises a plurality of etched forms wherein each of the etched forms is causing a local capacitive effect and a local inductive effect. The local capacitive effect and local inductive effect generates a plurality of local filters that reduce electrical noise. The intermediate sheet of dielectric material is bonded to the first conductive sheet, and the second conductive sheet is also bonded to the intermediate sheet.

Abstract translation: 用于降低电气噪声的蚀刻电容层压板。 蚀刻电容器层叠体被构造为印刷电路板的元件。 蚀刻电容器层叠体包括第一导电片，介电材料的中间片和第二导电片。 第一导电片还包括多个蚀刻形式，其中每个蚀刻形式引起局部电容效应和局部感应效应。 本地电容效应和局部感应效应产生多个降低电噪声的局部滤波器。 电介质材料的中间片与第一导电片接合，第二导电片也与中间片接合。