公开(公告)号：US20140157240A1

公开(公告)日：2014-06-05

申请号：US14233401

申请日：2011-07-20

Applicant: David Baca

Inventor： David Baca

IPC: G06F11/36

CPC classification number: G06F11/3624 ,  G06F11/3466 ,  G06F11/3612 ,  G06F11/3636 ,  G06F2201/865 ,  G06F2201/88

Abstract: A method of enabling an executed control flow path through computer program code to be determined. The method comprising modelling cumulative instruction counts for control flow paths through the computer program code, and inserting at least one probe within the computer program code to enable a cumulative instruction count value for at least one control flow path of the computer program code to be accessed.

Abstract translation: 能够确定通过计算机程序代码执行的控制流程的方法。 该方法包括对通过计算机程序代码的控制流程路径的累积指令计数进行建模，以及在计算机程序代码内插入至少一个探针，以使得能够访问计算机程序代码的至少一个控制流程路径的累积指令计数值 。

公开(公告)号：US20140143603A1

公开(公告)日：2014-05-22

申请号：US13683764

申请日：2012-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Steve McDuff

IPC: G06F11/36

CPC classification number: G06F11/36 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/3612 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88

Abstract: Execution statistics are gathered that represent results of execution of a validation check that evaluates code performance within an executing application. A determination is made as to whether the gathered execution statistics for the execution of the validation check match configured criteria to disable the validation check. The validation check is programmatically disabled in response to determining that the gathered execution statistics for the execution of the validation check match the configured criteria to disable the validation check.

Abstract translation: 收集执行统计信息，表示执行执行应用程序中的代码性能的验证检查的结果。 确定用于执行验证检查的所收集的执行统计信息是否匹配配置的标准以禁用验证检查。 响应确定执行验证检查的收集的执行统计信息与配置的标准匹配以禁用验证检查，以编程方式禁用验证检查。

公开(公告)号：US08732670B1

公开(公告)日：2014-05-20

申请号：US12826447

申请日：2010-06-29

Applicant: Jeffrey Daudel ,  Suman Cherukuri ,  Humberto Yeverino ,  Dickey Singh ,  Arpad Jakab ,  Marvin Justice ,  Jonathan Lindo

Inventor： Jeffrey Daudel ,  Suman Cherukuri ,  Humberto Yeverino ,  Dickey Singh ,  Arpad Jakab ,  Marvin Justice ,  Jonathan Lindo

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F9/45533 ,  G06F9/44521 ,  G06F9/44589 ,  G06F9/4484 ,  G06F9/45504 ,  G06F11/301 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/3636 ,  G06F2201/88

Abstract: Aspects of an application program's execution which might be subject to non-determinism are performed in a deterministic manner while the application program's execution is being recorded in a virtual machine environment so that the application program's behavior, when played back in that virtual machine environment, will duplicate the behavior that the application program exhibited when originally executed and recorded. Techniques disclosed herein take advantage of the recognition that only minimal data needs to be recorded in relation to the execution of deterministic operations, which actually can be repeated “verbatim” during replay, and that more highly detailed data should be recorded only in relation to non-deterministic operations, so that those non-deterministic operations can be deterministically simulated (rather than attempting to re-execute those operations under circumstances where the outcome of the re-execution might differ) based on the detailed data during replay.

Abstract translation: 在应用程序的执行被记录在虚拟机环境中时，可以以确定性的方式执行应用程序的执行可能受到非确定性的影响，使得应用程序在该虚拟机环境中回放时的行为将 复制应用程序在最初执行和记录时展现的行为。 本文中公开的技术利用了这样的认识：只有最小数据需要与确定性操作的执行相关才能被记录，确实性操作实际上可以在重放期间“逐字地”重复，并且更高度详细的数据应该只记录在非 - 确定性操作，以便可以确定性地模拟那些非确定性操作（而不是在重新执行的结果可能不同的情况下尝试重新执行这些操作），这取决于重放期间的详细数据。

公开(公告)号：US20140122801A1

公开(公告)日：2014-05-01

申请号：US13663335

申请日：2012-10-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel LOH ,  James O'CONNOR

IPC: G06F12/14 ,  G06F12/08

CPC classification number: G06F11/3433 ,  G06F11/349 ,  G06F13/1663 ,  G06F2201/86 ,  G06F2201/88

Abstract: Embodiments are described for a method for controlling access to memory in a processor-based system comprising monitoring a number of interference events, such as bank contentions, bus contentions, row-buffer conflicts, and increased write-to-read turnaround time caused by a first core in the processor-based system that causes a delay in access to the memory by a second core in the processor-based system; deriving a control signal based on the number of interference events; and transmitting the control signal to one or more resources of the processor-based system to reduce the number of interference events from an original number of interference events.

Abstract translation: 描述了用于在基于处理器的系统中控制对存储器的访问的方法的实施例，包括监视多个干扰事件，例如银行争用，总线争用，行缓冲器冲突以及由 基于处理器的系统中的第一核心，其导致在基于处理器的系统中由第二核心访问存储器的延迟; 基于干扰事件的数量导出控制信号; 以及将所述控制信号发送到所述基于处理器的系统的一个或多个资源，以从原始数量的干扰事件减少干扰事件的数量。

公开(公告)号：US08694728B2

公开(公告)日：2014-04-08

申请号：US12942765

申请日：2010-11-09

Applicant: Carl A. Waldspurger ,  Rajesh Venkatasubramanian ,  Alexander Thomas Garthwaite ,  Yury Baskakov ,  Puneet Zaroo

Inventor： Carl A. Waldspurger ,  Rajesh Venkatasubramanian ,  Alexander Thomas Garthwaite ,  Yury Baskakov ,  Puneet Zaroo

IPC: G06F12/00

CPC classification number: G06F12/122 ,  G06F9/45558 ,  G06F11/3471 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2201/815 ,  G06F2201/88

Abstract: Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient technique includes the steps of selecting a subset of memory pages for the workload, maintaining a least recently used (LRU) data structure for the selected memory pages, detecting accesses to the selected memory pages and updating the LRU data structure in response to the detected accesses, and generating data for constructing a miss-rate curve for the workload using the LRU data structure. After a memory page is accessed, the memory page may be left untraced for a period of time, after which the memory page is retraced.

Abstract translation: 错误率曲线以资源有效的方式构建，以便可以构建它们，并且可以在工作负载运行时进行内存管理决策。 资源有效的技术包括以下步骤：为工作负载选择存储器页面的子集，维护所选择的存储器页面的最近最少使用的（LRU）数据结构，检测对所选择的存储器页面的访问以及响应地更新LRU数据结构 并且使用LRU数据结构生成用于构建工作负载的错过率曲线的数据。 在访问存储器页面之后，存储器页面可以保持未被跟踪一段时间，之后再回读存储器页面。

公开(公告)号：US08671267B2

公开(公告)日：2014-03-11

申请号：US12822359

申请日：2010-06-24

Applicant: Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Christine C. Jones ,  Arthur J. O'Neill, Jr. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

Inventor： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Christine C. Jones ,  Arthur J. O'Neill, Jr. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

IPC: G06F9/30 ,  G06F9/40 ,  G06F13/00 ,  G06F3/00

CPC classification number: G06F9/3867 ,  G06F11/3419 ,  G06F11/3466 ,  G06F2201/88

Abstract: A pipelined processing device includes: a device controller configured to receive a request to perform an operation; a plurality of subcontrollers configured to receive at least one instruction associated with the operation, each of the plurality of subcontrollers including a counter configured to generate an active time value indicating at least a portion of a time taken to process the at least one instruction; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor configured to receive the active time value; and a shared pipeline storage area configured to store the active time value for each of the plurality of subcontrollers.

Abstract translation: 流水线处理装置包括：设备控制器，被配置为接收执行操作的请求; 多个子控制器被配置为接收与所述操作相关联的至少一个指令，所述多个子控制器中的每一个包括配置成生成指示处理所述至少一个指令所花费的时间的至少一部分的活动时间值的计数器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器被配置为接收所述活动时间值; 以及共享流水线存储区域，被配置为存储多个子控制器中的每一个的活动时间值。

公开(公告)号：US08667220B2

公开(公告)日：2014-03-04

申请号：US13378312

申请日：2011-05-30

Applicant: Takanori Sato ,  Takato Kusama

Inventor： Takanori Sato ,  Takato Kusama

IPC: G06F12/00

CPC classification number: G06F3/061 ,  G06F3/0647 ,  G06F3/067 ,  G06F3/0685 ,  G06F11/3433 ,  G06F11/3485 ,  G06F12/0866 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/1016 ,  G06F2212/222 ,  G06F2212/224 ,  G06F2212/281 ,  G06F2212/314

Abstract: The present invention measures an actual utilization frequency of data and controls a location of this data in a storage apparatus in a case where a host computer makes joint use of a storage apparatus and a cache apparatus. A portion of data used by an application program 1A is stored in a storage apparatus 2 and a cache apparatus 3. A management apparatus 4 detects an I/O load of a page (4A), and detects an I/O load of cache data (4B). The management apparatus 4 determines a corresponding relationship between the page and the cache data (4C), and adds the I/O load of the cache data to the I/O load of the page.

Abstract translation: 本发明在主计算机共同使用存储装置和缓存装置的情况下，测量数据的实际使用频率并控制该数据在存储装置中的位置。 应用程序1A使用的数据的一部分被存储在存储装置2和高速缓存装置3中。管理装置4检测页面的I / O负载（4A），并检测缓存数据的I / O负载 （4B）。 管理装置4确定页面和高速缓存数据（4C）之间的对应关系，并且将缓存数据的I / O负载添加到页面的I / O负载。

公开(公告)号：US20140053155A1

公开(公告)日：2014-02-20

申请号：US14060947

申请日：2013-10-23

Applicant: Erik C. Cota-Robles ,  Gilbert Neiger ,  Steven M. Bennett ,  Andrew V. Anderson

Inventor： Erik C. Cota-Robles ,  Gilbert Neiger ,  Steven M. Bennett ,  Andrew V. Anderson

IPC: G06F9/455

CPC classification number: G06F9/45533 ,  G06F9/455 ,  G06F9/45558 ,  G06F9/46 ,  G06F9/461 ,  G06F9/462 ,  G06F9/468 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/348 ,  G06F2009/45591 ,  G06F2201/815 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: Embodiments of apparatuses, methods, and systems for virtualizing performance counters are disclosed. In one embodiment, an apparatus includes a counter, a counter enable storage location, counter enable logic, and virtual machine control logic. The counter enable storage location is to store a counter enable indicator. The counter enable logic is to enable the counter based on the counter enable indicator. The virtual machine control logic is to transfer control of the apparatus to a guest. The virtual machine control logic includes guest state load logic to cause a guest value from a virtual machine control structure to be loaded into the counter enable storage location in connection with a transfer of control of the apparatus to the guest.

Abstract translation: 公开了用于虚拟化性能计数器的装置，方法和系统的实施例。 在一个实施例中，装置包括计数器，计数器使能存储位置，计数器使能逻辑和虚拟机器控制逻辑。 计数器使能存储位置是存储计数器使能指示符。 计数器使能逻辑是基于计数器使能指示器启用计数器。 虚拟机控制逻辑是将设备的控制传送给客人。 虚拟机控制逻辑包括客户端状态负载逻辑，以使来自虚拟机控制结构的客户值被加载到计数器使能存储位置中，并将该设备的控制转移给客户端。

公开(公告)号：US08656411B2

公开(公告)日：2014-02-18

申请号：US12042992

申请日：2008-03-05

Applicant: Lance E. Hacking

Inventor： Lance E. Hacking

IPC: G06F9/44 ,  G06F9/46

CPC classification number: G06F9/542 ,  G06F11/30 ,  G06F11/3466 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: A technique to monitor events within a computer system or integrated circuit. In one embodiment, a software-accessible event monitoring storage and hardware-specific monitoring logic are selectable and their corresponding outputs may be monitored by accessing a counter to count events corresponding to each of software-accessible storage and hardware-specific monitoring logic.

Abstract translation: 监控计算机系统或集成电路中的事件的技术。 在一个实施例中，可以选择软件可访问事件监视存储和硬件特定的监视逻辑，并且可以通过访问计数器来监视其对应的输出，以计数与软件可访问的存储和硬件特定的监视逻辑中的每一个对应的事件。

公开(公告)号：US08639857B2

公开(公告)日：2014-01-28

申请号：US13848992

申请日：2013-03-22

Applicant: International Business Machines Corporation

Inventor： Scott M Carlson ,  Greg A. Dyck ,  Tan Lu ,  Kenneth J. Oakes ,  Dale F. Riedy, Jr. ,  William J. Rooney ,  John S. Trotter ,  Leslie W. Wyman ,  Harry M. Yudenfriend

IPC: G06F3/00 ,  G01R15/00 ,  G06F17/50

CPC classification number: G06F13/105 ,  G06F3/0653 ,  G06F9/30003 ,  G06F11/3041 ,  G06F11/3065 ,  G06F11/3419 ,  G06F11/3485 ,  G06F13/124 ,  G06F13/24 ,  G06F17/5036 ,  G06F2201/88 ,  H04L1/0073

Abstract: An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.

Abstract translation: 提供扩展输入/输出（I / O）测量字设备。 提供扩展I / O测量字设施的仿真。 该设施提供在与I / O响应块相关联的扩展测量字中存储与单个I / O操作相关联的测量数据。 在另一方面，所存储的数据可以具有大约半微秒的分辨率。