公开(公告)号：US20150107880A1

公开(公告)日：2015-04-23

申请号：US14319743

申请日：2014-06-30

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Hye Jin KIM ,  Hyo Seung Nam ,  Tae Hong Min ,  Sang Hoon Kim ,  Suk Hyeon Cho ,  Jung Han Lee

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/185 ,  H05K3/429 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/0979

Abstract: Disclosed herein is a multilayer printed circuit board. The multilayer printed circuit board according to the present invention includes: a stack via stacked in an upper portion of a core layer; staggered vias formed at both sides of the stack via and stacked on the core layer; and a solder resist layer stacked in a lower portion of the core layer and stacked on an insulating film except for open regions of the stack via and the staggered vias, such that the plurality of vias formed in the staggered via may increase rigidity to prevent warpage of the multilayer printed circuit board from being generated.

Abstract translation: 这里公开了一种多层印刷电路板。 根据本发明的多层印刷电路板包括：堆叠体，堆叠在芯层的上部; 形成在堆叠的两侧的交错通孔并堆叠在芯层上; 以及堆叠在芯层的下部并且堆叠在除了堆叠通孔的开口区域和交错通孔之外的绝缘膜上的阻焊层，使得形成在交错通孔中的多个通孔可以增加刚性以防止翘曲 的多层印刷电路板。

公开(公告)号：US08975530B2

公开(公告)日：2015-03-10

申请号：US13669472

申请日：2012-11-06

Applicant: Hui-Hsuan Chou ,  Shih-Ming Huang

Inventor： Hui-Hsuan Chou ,  Shih-Ming Huang

IPC: H05K1/09 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0265 ,  H05K1/111 ,  H05K2201/0979

Abstract: A printed circuit board (PCB) includes a substrate, a pad, a plurality of connecting wires and a plurality of separating portions. The pad arranged on at least one surface of the substrate. The plurality of connecting wires increase contact area of the pad and a copper foil around the pad to keep the current of the PCB steady when a lot of current flow through the PCB. The plurality of separating portions located on between the pad and the copper foil around the pad to divide the pad and the copper foil to avoid short-circuit when the copper foil is etched.

Abstract translation: 印刷电路板（PCB）包括基板，焊盘，多个连接线和多个分离部分。 衬垫布置在衬底的至少一个表面上。 当多个电流流过PCB时，多个连接线增加焊盘和焊盘周围的铜箔的接触面积，以保持PCB的电流稳定。 多个分离部分位于衬垫和铜箔之间，围绕衬垫分隔衬垫和铜箔，以避免当铜箔被蚀刻时短路。

公开(公告)号：US20150041835A1

公开(公告)日：2015-02-12

申请号：US14521105

申请日：2014-10-22

Applicant: Sharp Kabushiki Kaisha

Inventor： Makoto AGATANI ,  Toshio Hata ,  Tomokazu Nada ,  Shinya Ishizaki

IPC: H01L33/62 ,  H01L33/54 ,  H01L25/075

CPC classification number: H01L25/0753 ,  F21K9/00 ,  F21K9/232 ,  F21V23/06 ,  F21Y2101/00 ,  F21Y2105/10 ,  F21Y2115/10 ,  H01L33/483 ,  H01L33/52 ,  H01L33/54 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/01327 ,  H01L2933/0066 ,  H05K1/11 ,  H05K2201/0391 ,  H05K2201/094 ,  H05K2201/0979 ,  H05K2201/10106 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A light-emitting device capable of ensuring an electric connection between a light-emitting element and an electrode without generating any problem in practical use, by both connecting methods with a solder and a connector, and a lighting device provided with the light-emitting device are provided. The light-emitting device according to the present invention has a plurality of LED chips, and a soldering electrode land and a connector connecting electrode land electrically connected to the chips, on a ceramic substrate. The soldering electrode land is formed of a first conductive material having a function to prevent diffusion to a solder, and the connector connecting electrode land is formed of a second conductive material having a function to prevent oxidation.

Abstract translation: 一种能够确保发光元件和电极之间的电连接而不会在实际使用中产生任何问题的发光装置，通过两种连接方法与焊料和连接器，以及设置有发光装置的照明装置 被提供。 根据本发明的发光装置在陶瓷基板上具有多个LED芯片，以及焊接电极焊盘和与芯片电连接的连接器连接电极焊盘。 焊接电极焊盘由具有防止向焊料扩散的功能的第一导电材料形成，并且连接器连接电极焊盘由具有防止氧化功能的第二导电材料形成。

公开(公告)号：US20150027762A1

公开(公告)日：2015-01-29

申请号：US14444144

申请日：2014-07-28

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Sang SHIN ,  Joo Sung PARK

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K1/0271 ,  H05K1/112 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/09527 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/0979

Abstract: Disclosed herein is a printed circuit board capable of increasing reliability by decreasing stress between an insulating layer and solder balls. The printed circuit board includes: an insulating layer part including circuit patterns and connecting lands having solder balls seated thereon and including a plurality of insulating layers; a plurality of connecting pads and non-connecting pads formed at the insulating layer part; and a plurality of reinforcing vias formed in the non-connecting pads and reinforcing a close adhesion state between the insulating layer part and the non-connecting pads.

Abstract translation: 这里公开了能够通过降低绝缘层和焊球之间的应力来提高可靠性的印刷电路板。 印刷电路板包括：包括电路图案的绝缘层部分和其上安装有焊球并且包括多个绝缘层的连接焊盘; 多个连接焊盘和形成在绝缘层部分的非连接焊盘; 以及形成在所述非连接焊盘中的多个加强通孔，并且在所述绝缘层部分和所述非连接焊盘之间增强紧密粘合状态。

公开(公告)号：US20140367152A1

公开(公告)日：2014-12-18

申请号：US14259011

申请日：2014-04-22

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Byoung Hwa LEE ,  Heung Kil PARK ,  Kyo Kwang LEE ,  Young Ghyu AHN ,  Sang Soo PARK ,  Soon Ju LEE

IPC: H05K1/11 ,  H01G4/30

CPC classification number: H05K1/111 ,  H01G4/12 ,  H01G4/1209 ,  H01G4/232 ,  H01G4/30 ,  H05K3/3442 ,  H05K2201/09709 ,  H05K2201/0979 ,  H05K2201/10015 ,  H05K2201/2045 ,  Y02P70/611

Abstract: A multilayer ceramic capacitor may include: a ceramic body including dielectric layers and having first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other; an active layer configured to form capacitance by including first and second internal electrodes facing each other with one dielectric layer therebetween and alternately exposed to the first or second side surface; upper and lower cover layers disposed on and below the active layer; and a first external electrode disposed on the first side surface and a second external electrode disposed on the second side surface. Thickness T and width W of the ceramic body satisfy 0.75W≦T≦1.25W, gap G between the first and second external electrodes satisfies 30 μm≦G≦0.9W, and an average number of dielectric grains in a single dielectric layer in a thickness direction thereof is 2 or greater.

Abstract translation: 多层陶瓷电容器可以包括：陶瓷体，其包括电介质层，并且具有彼此相对的第一和第二主表面，彼此相对的第一和第二侧表面以及彼此相对的第一和第二端面; 有源层，被配置为通过包括彼此面对的第一和第二内部电极并且在其间具有一个介电层并交替地暴露于第一或第二侧表面而形成电容; 设置在有源层上和下面的上和下覆盖层; 以及设置在第一侧表面上的第一外部电极和设置在第二侧表面上的第二外部电极。 陶瓷体的厚度T和宽度W满足0.75W＆nlE; T＆nlE; 1.25W，第一和第二外部电极之间的间隙G满足30μm＆lt; NlE; G＆nlE; 0.9W，以及单个介电层中的平均电介质颗粒数 厚度方向为2以上。

公开(公告)号：US08907228B2

公开(公告)日：2014-12-09

申请号：US13411650

申请日：2012-03-05

Applicant: Wen-Fu Huang ,  Shih-Ching Chen ,  Chen-Hui Cheng ,  Meng-Hsueh Wu

Inventor： Wen-Fu Huang ,  Shih-Ching Chen ,  Chen-Hui Cheng ,  Meng-Hsueh Wu

IPC: H05K1/11 ,  H05K3/02 ,  H05K3/10

CPC classification number: G06F3/041 ,  G06F3/044 ,  G06F2203/04103 ,  H05K1/0296 ,  H05K2201/0979 ,  Y10T29/49155

Abstract: The present disclosure related to circuit structure of an electronic device, wherein the circuit structure comprises of a main line formed on a substrate; and at least an auxiliary line electrically connected to the main line to form a conductive return circuit used for a signal to pass through the auxiliary line when the main line is disconnected. Addition of the auxiliary line avoids any breaking of signal transmission due to partial disconnection of the main line. The present disclosure also relates to a method for manufacturing the circuit structure, wherein the method simplifies the manufacturing process and also reduces the rate of deformation or disconnection of lines.

Abstract translation: 本公开涉及电子设备的电路结构，其中电路结构包括形成在基板上的主线; 以及至少一个辅助线路，其电连接到所述主线路，以形成当所述主线路断开时用于信号通过所述辅助线路的导电返回电路。 辅助线路的添加可避免由于主线部分断开导致信号传输的任何破坏。 本公开还涉及一种用于制造电路结构的方法，其中该方法简化了制造过程并且还降低了线的变形或断开的速率。

公开(公告)号：US20140305688A1

公开(公告)日：2014-10-16

申请号：US14250211

申请日：2014-04-10

Applicant: CANON KABUSHIKI KAISHA

Inventor： Shoji Matsumoto ,  Seiji Hayashi ,  Takuya Kondo

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/115 ,  H05K1/0251 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/10545

Abstract: A printed wiring board includes a first conductive layer, a second conductive layer arranged at a gap with respective to the first conductive layer, a third conductive layer, a first via conductor and a second via conductor, and a third signal wiring pattern. A first signal wiring pattern is arranged on the first conductive layer, a second signal wiring pattern is arranged on the second conductive layer, and a third signal wiring pattern that is arranged on the third conductive layer. The third conductive layer is arranged between the first conductive layer and the second conductive layer via an insulating layer. The first via conductor and the second via conductor, which are arranged to be mutually adjacent, connect the first signal wiring pattern to the second signal wiring pattern. The third signal wiring pattern connects the first via conductor to the second via conductor.

Abstract translation: 印刷布线板包括：第一导电层，与第一导电层相对配置的间隙的第二导电层，第三导电层，第一通孔导体和第二通路导体以及第三信号布线图案。 第一信号布线图案布置在第一导电层上，第二信号布线图案布置在第二导电层上，第三信号布线图案布置在第三导电层上。 第三导电层通过绝缘层布置在第一导电层和第二导电层之间。 布置成相互相邻的第一通孔导体和第二通孔导体将第一信号布线图案连接到第二信号布线图案。 第三信号布线图案将第一通孔导体连接到第二通孔导体。

公开(公告)号：US08723052B1

公开(公告)日：2014-05-13

申请号：US13778415

申请日：2013-02-27

Applicant: Boulder Wind Power, Inc.

Inventor： Brian Sullivan ,  Stephane Eisen

IPC: H05K1/11

CPC classification number: H05K1/0201 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/0265 ,  H05K1/0298 ,  H05K2201/09727 ,  H05K2201/0979

Abstract: In some embodiments, a system includes a conductor on a first layer of a laminated composite assembly. The laminated composite assembly has an input, an output, a first electrical interconnect which couples the conductor on the first layer of the laminated composite assembly with a second conductor on a second layer of the laminated composite assembly, and a second electrical interconnect which electrically couples the first conductor with the second conductor. A width of the second electrical interconnect is greater than a width of the first electrical interconnect. A resistance of the laminated composite assembly as measured between the electrical input and the electrical output is less than the resistance of the laminated composite assembly as measured between the electrical input and the electrical output if the width of the first electrical interconnect were substantially equal to the width of the second electrical interconnect.

Abstract translation: 在一些实施例中，系统包括层压复合组件的第一层上的导体。 层压复合组件具有输入，输出，第一电互连，其将层压复合组件的第一层上的导体与叠层复合组件的第二层上的第二导体耦合，以及电耦合的第二电互连 第一个导体与第二个导体。 第二电互连的宽度大于第一电互连的宽度。 在电输入和电输出之间测量的层压复合组件的电阻小于在电输入和电输出之间测量的层压复合组件的电阻，如果第一电互连的宽度基本上等于 第二电互连的宽度。

公开(公告)号：US20140104747A1

公开(公告)日：2014-04-17

申请号：US14042637

申请日：2013-09-30

Applicant: X2Y ATTENUATORS, LLC

Inventor： William M. Anthony ,  David Anthony ,  Anthony Anthony

IPC: H01G4/35 ,  H01G4/30

CPC classification number: H01G4/35 ,  H01G4/005 ,  H01G4/232 ,  H01G4/30 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/43 ,  Y10T29/49002

Abstract: The application discloses novel internal structures of energy conditioners, assemblies of external structures of energy conditioners and mounting structure, and novel circuits including energy conditioners having A, B, and G master electrodes.

Abstract translation: 该申请公开了能量调节器的新型内部结构，能量调节器的外部结构的组件和安装结构，以及包括具有A，B和G主电极的能量调节器的新颖的电路。

公开(公告)号：US20140084955A1

公开(公告)日：2014-03-27

申请号：US13837600

申请日：2013-03-15

Applicant: CHUNGHWA PRECISION TEST TECH CO., LTD.

Inventor： YUAN-CHIANG TENG ,  KAI-CHIEH HSIEH ,  WEN-TSUNG LEE

IPC: G01R1/04 ,  H05K1/09

CPC classification number: G01R1/0491 ,  G01R1/07378 ,  H05K1/0298 ,  H05K1/09 ,  H05K3/4644 ,  H05K2201/09254 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/10378

Abstract: A fine pitch interposer structure includes a Multi-core base substrate and a plurality of buildup laminates. A surface of each Multi-core base substrate has a first circuit layer, and a second circuit layer which is electrically connected to the first circuit layer. The buildup laminates are stacked on the surface of the Multi-core base substrate. Each buildup laminate includes a photosensitive dielectric layer, and a plurality of blind vias with a pre-determined interval therebetween which are correspondingly arranged on each of the plurality of vias formed on the photosensitive dielectric layer. The blind vias are electrically connected to the first circuit layer. At least one blind via of one buildup laminate is superimposed on another blind via of another buildup laminate.

Abstract translation: 细间距插入器结构包括多芯基底和多个积层叠层。 每个多芯基底基板的表面具有第一电路层和电连接到第一电路层的第二电路层。 堆叠层叠体堆叠在多芯基底的表面上。 每个积层叠层包括光敏介电层，并且在它们之间具有预定间隔的多个盲孔相应地布置在形成在光敏介电层上的多个通孔中的每一个上。 盲通孔电连接到第一电路层。 至少一个通过一个堆叠层压板的盲孔叠加在另一个堆积层压板的另一盲孔上。