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    Wet etched insulator and electronic circuit component
    161.
    发明申请
    Wet etched insulator and electronic circuit component 失效
    湿式蚀刻绝缘子和电子电路元件

    公开(公告)号：US20030085451A1

    公开(公告)日：2003-05-08

    申请号：US10074224

    申请日：2002-06-10

    Applicant: Dai Nippon Printing Co., Ltd.

    Inventor： Katsuya Sakayori ,  Terutoshi Momose ,  Shigeki Kawano ,  Tomoko Togashi ,  Hiroko Amasaki ,  Nobuhiro Sakihama ,  Tsuyoshi Yamazaki ,  Michiaki Uchiyama ,  Hiroshi Yagi

    IPC: H01L021/00 ,  H01L023/58

    CPC classification number: H01L21/31138 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/32134 ,  H05K1/0346 ,  H05K1/056 ,  H05K3/002 ,  H05K3/064 ,  H05K2201/0154 ,  H05K2201/0166

    Abstract: The present invention relates to an insulator as an insulating layer in a laminate which can inhibit dusting at the time of use, more particularly an electronic circuit component to which the insulator has been applied, particularly a wireless suspension. The insulator comprises a laminate of one or more insulation unit layers etchable by a wet process, the insulator having been subjected to plasma treatment after wet etching. The insulator exists mainly as an insulating layer in a laminate having a layer construction of first inorganic material layernullinsulating layernullsecond inorganic material layer or a layer construction of inorganic material layernullinsulating layer, and at least a part of the inorganic material layer has been removed to expose the insulating layer.

    Abstract translation: 本发明涉及一种层叠体中的绝缘体，其可以在使用时抑制除尘，更具体地说，涉及绝缘体的电子电路部件，特别是无线悬架。 绝缘体包括可通过湿法蚀刻的一个或多个绝缘单元层的层压体，该绝缘体在湿蚀刻之后已进行等离子体处理。 绝缘体主要作为具有第一无机材料层 - 绝缘层 - 第二无机材料层的层结构或无机材料层 - 绝缘层的层结构的层叠体的绝缘体存在，并且至少一部分无机材料层 已经被去除以暴露绝缘层。

    Processes for manufacturing multilayer flexible wiring boards
    163.
    发明申请
    Processes for manufacturing multilayer flexible wiring boards 有权
    制造多层柔性布线板的工艺

    公开(公告)号：US20020079134A1

    公开(公告)日：2002-06-27

    申请号：US10028624

    申请日：2001-12-20

    Inventor： Yutaka Kaneda

    IPC: H05K001/16 ,  H05K003/02

    CPC classification number: H05K3/0002 ,  H05K1/0393 ,  H05K3/002 ,  H05K3/0082 ,  H05K3/064 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/4614 ,  H05K3/4635 ,  H05K2201/0166 ,  H05K2201/0367 ,  H05K2203/056 ,  H05K2203/0733 ,  H05K2203/1545 ,  Y10S428/901 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

    Abstract: In one embodiment, the present invention provides a process for manufacturing a multilayer flexible wiring board, which allows individual layers of wiring boards to be precisely positioned and to be readily stacked. A mask for exposure is prepared in which a plurality of pattern holes corresponding to individual layers of wiring boards of a multilayer flexible wiring board are arranged in the direction perpendicular to the transporting direction P of substrate. This mask for exposure is used to form a plurality of wiring patterns corresponding to individual layers of wiring boards of a multilayer flexible wiring board on the same sheet-like substrate.

    Abstract translation: 在一个实施例中，本发明提供一种制造多层挠性布线板的方法，其允许各层布线板精确定位并容易堆叠。 制备用于曝光的掩模，其中与垂直于基板的传送方向P的方向布置与多层柔性布线板的布线板的各层相对应的多个图案孔。 该曝光用掩模用于形成与同一片状基板上的多层柔性布线基板的各层布线基板对应的多个布线图案。

    Process of manufacturing thin ball grid array substrates
    165.
    发明授权
    Process of manufacturing thin ball grid array substrates 失效
    制造薄球栅阵列基板的工艺

    公开(公告)号：US06274491B1

    公开(公告)日：2001-08-14

    申请号：US09636315

    申请日：2000-08-11

    Applicant: Wan Le Xie ,  Fu Yu Huang ,  Yung-Cheng Chuang ,  Ning Huang ,  Chung Ming Chang ,  Hui-Pin Chen ,  Chia-Chieh Hu ,  Feng Chang Tu ,  Hsuan Jui Chang ,  Hua Wen Chiang

    Inventor： Wan Le Xie ,  Fu Yu Huang ,  Yung-Cheng Chuang ,  Ning Huang ,  Chung Ming Chang ,  Hui-Pin Chen ,  Chia-Chieh Hu ,  Feng Chang Tu ,  Hsuan Jui Chang ,  Hua Wen Chiang

    IPC: H01L2144

    CPC classification number: H05K3/4092 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K3/002 ,  H05K3/062 ,  H05K3/108 ,  H05K3/3473 ,  H05K2201/0154 ,  H05K2201/0166 ,  H05K2201/0394 ,  H01L2924/00

    Abstract: A process of manufacturing thin ball array substrates includes the steps of: using a layer of polyimide film as a carrier, electroplating a thin copper layer on the polyimide film, electroplating a thick copper layer on the thin copper layer, applying photosensitive coating layers on both sides of the carrier, mounting two masks with optically transmissible circuit tracks on two sides of the carrier and then processing the carrier with exposure treatment, processing the carrier with development treatment so as to remove the photosensitive coating layers aligned with the circuit track thereby forming recessed circuit tracks on the photosensitive coating layers, electroplating a copper layer on a top of the carrier thereby forming an additional copper layer on the thick copper layer, etching a bottom of the carrier to remove the upper recessed circuit track thereon, coating the copper layer on the upper recessed circuit track with soldering metallic material so as to make a top of the soldering metallic material, washing away the photosensitive coating layers with chemical agent, and removing surplus copper layer to remain in circuit lines and the soldering metallic material, whereby a thin ball grid array substrate with thicker circuit lines without remaining electroplating lines can be obtained.

    Abstract translation: 制造薄球阵列基板的方法包括以下步骤：使用聚酰亚胺膜作为载体，在聚酰亚胺膜上电镀薄铜层，在薄铜层上电镀厚铜层，在两层上施加感光涂层 在载体的两侧安装具有光学传输电路轨道的两个掩模，然后用曝光处理处理载体，通过显影处理处理载体，以除去与电路轨迹对准的感光涂层，从而形成凹陷 在光敏涂层上的电路轨迹，在载体的顶部上电镀铜层，从而在厚铜层上形成附加的铜层，蚀刻载体的底部以除去其上的凹陷电路轨道，将铜层涂覆在 具有焊接金属材料的上凹形电路轨道，以便形成顶部 用化学试剂洗涤光敏涂层，除去多余的铜层，保留在电路线和焊接金属材料中，从而可以获得具有较厚电路线而不残留电镀线的薄球栅阵列基板。

    Thin laminated microstructure with precisely aligned openings
    169.
    发明授权
    Thin laminated microstructure with precisely aligned openings 失效
    具有精确对准开口的薄层压微结构

    公开(公告)号：US5698299A

    公开(公告)日：1997-12-16

    申请号：US437375

    申请日：1995-05-09

    Applicant: Walter Schmidt ,  Marco Martinelli ,  Alexandra Frei

    Inventor： Walter Schmidt ,  Marco Martinelli ,  Alexandra Frei

    IPC: B01D39/16 ,  B01D67/00 ,  B01D69/12 ,  B07B1/46 ,  B81B1/00 ,  G02B6/122 ,  G02B6/36 ,  G02B6/42 ,  H05K1/02 ,  B32B9/00

    CPC classification number: B07B1/4618 ,  B01D39/1692 ,  B01D67/0058 ,  B01D69/12 ,  B07B1/4663 ,  G02B6/122 ,  G02B6/4228 ,  H05K1/0272 ,  G02B6/423 ,  H05K2201/0166 ,  H05K2201/064 ,  H05K2201/09509 ,  H05K2203/0554 ,  Y10T29/49165 ,  Y10T428/24826 ,  Y10T428/24917

    Abstract: A multilayer laminated body has a determinate system of hollow passages and is formed by an assembly of flat layers of polymeric materials having major dimensions in orthogonal X and Y directions and a thickness dimension in a Z direction perpendicular to the X and Y directions. Selected ones of the layers have openings extending through in the Z direction, and other layers have canals formed in an X-Y plane. The openings and canals form parts of hollow passages so that assembly of multiple layers joins openings and canals forms complete and continuous passages through the assembled layers. Layers joined in pre-laminate assemblies are assembled together in precise relative positions for desired alignment of the canals and openings. The passages can be filled with optically conductive material or electrically conductive material and electrodes can be appropriately positioned for acting on fluids passing through the body.

    Abstract translation: 多层层叠体具有确定的中空通道系统，并且通过具有垂直于X和Y方向的主要尺寸的聚合物材料的平面组合和垂直于X和Y方向的Z方向上的厚度尺寸的组合形成。 所选择的层具有沿Z方向延伸的开口，而其它层具有在X-Y平面中形成的通道。 开口和沟渠形成中空通道的部分，使得多个层的组合连接开口和沟渠，形成通过组装层的完整且连续的通道。 连接在预层压组件中的层在精确的相对位置组装在一起，用于期望对准运河和开口。 通道可以用光学导电材料或导电材料填充，并且电极可以适当地定位以作用于穿过身体的流体。

    Laminate for insulation protection of circuit boards
    170.
    发明授权
    Laminate for insulation protection of circuit boards 失效
    电路板绝缘保护层压板

    公开(公告)号：US5601905A

    公开(公告)日：1997-02-11

    申请号：US395516

    申请日：1995-02-27

    Applicant: Hisashi Watanabe ,  Takashi Tanaka ,  Kaoru Okamoto ,  Keiji Yoshizawa ,  Hiroyuki Chinju ,  Isamu Takarabe

    Inventor： Hisashi Watanabe ,  Takashi Tanaka ,  Kaoru Okamoto ,  Keiji Yoshizawa ,  Hiroyuki Chinju ,  Isamu Takarabe

    IPC: G03F7/09 ,  H05K3/28 ,  B32B7/02 ,  B32B27/08 ,  C08G73/10

    CPC classification number: G03F7/094 ,  H05K3/28 ,  H05K2201/0154 ,  H05K2201/0166 ,  H05K2203/0582 ,  H05K2203/0585 ,  H05K2203/066 ,  Y10S428/901 ,  Y10T428/2495 ,  Y10T428/24967 ,  Y10T428/26 ,  Y10T428/2839 ,  Y10T428/31721

    Abstract: A laminate comprising at least two layers of a photosensitive resin layer and a polyimide precursor resin layer; a process for formation of an insulating protective layer using a laminate which comprises laminating a laminate comprising at least photosensitive resin layer and a polyimide precursor resin layer on an insulating board having an exposed circuit; selectively exposing the photosensitive resin layer to active light; developing the resultant photosensitive resin layer; removing the exposed polyimide precursor resin layer by etching it with an alkaline solution using the photosensitive resin layer as a mask; removing the photosensitive resin layer; and then curing the residual polyimide precusor resin layer; and a process for preparation of a printed circuit which comprises forming a polymide precursor resin layer on an insulating board having an exposed circuit, patterning the resin layer with an alkaline solution, and then curing it.The laminate of this invention can provide extremely easily an insulating protective layer for circuits having a high processing precision and excellent in reliability on insulation. Further, a printed circuit having a high processing precision and excellent in reliability on insulation can be provided extremely easily by the processes of this invention.

    Abstract translation: 包含至少两层感光性树脂层和聚酰亚胺前体树脂层的层压体; 使用层压体形成绝缘保护层的方法，该方法包括在具有暴露电路的绝缘板上层叠至少包含感光性树脂层和聚酰亚胺前体树脂层的层压体; 将感光性树脂层选择性曝光为活性光; 显影所得的感光性树脂层; 通过使用感光性树脂层作为掩模，用碱性溶液蚀刻曝光的聚酰亚胺前体树脂层; 去除感光性树脂层; 然后固化残留的聚酰亚胺前体树脂层; 以及制造印刷电路的方法，包括在具有暴露电路的绝缘板上形成聚酰亚胺前体树脂层，用碱溶液对树脂层进行图案化，然后固化。 本发明的层叠体可以非常容易地提供具有高加工精度和绝缘可靠性优异的电路的绝缘保护层。 此外，通过本发明的方法，可以非常容易地提供具有高加工精度和绝缘可靠性优异的印刷电路。

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