公开(公告)号：US08071160B2

公开(公告)日：2011-12-06

申请号：US12115874

申请日：2008-05-06

Applicant: Jeffrey D. Chinn ,  Robert W. Ashurst ,  Adam N. Anderson

Inventor： Jeffrey D. Chinn ,  Robert W. Ashurst ,  Adam N. Anderson

IPC: B05D5/12 ,  H05K3/00 ,  C23C16/00

CPC classification number: H05K3/284 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K2201/0209 ,  H05K2201/0239 ,  H05K2201/0257 ,  H05K2201/09872 ,  Y10T428/24355 ,  Y10T428/24364 ,  Y10T428/24372 ,  Y10T428/24388 ,  Y10T428/24405 ,  Y10T428/24413 ,  Y10T428/24421 ,  Y10T428/269 ,  Y10T428/2839 ,  H01L2924/00

Abstract: A method of forming a film is provided. Nanoparticles are deposited on a surface of a substrate using a liquid deposition process. The nanoparticles are linked to each other and to the surface using linker molecules. A coating having a surface energy of less than 70 dyne/cm is deposited over the film to form a coated film. The coated film has an RMS surface roughness of 25 nm to 500 nm, a film coverage of 25% to 60%, a surface energy of less than 70 dyne/cm; and a durability of 10 to 5000 microNewtons. Depending on the particular environment in which the film is to be used, a durability of 10 to 500 microNewtons may be preferred. A film thickness 3 to 100 times the RMS surface roughness of the film is preferred.

Abstract translation: 提供了一种形成膜的方法。 使用液体沉积工艺将纳米颗粒沉积在基底的表面上。 使用接头分子将纳米颗粒彼此连接并连接到表面。 表面能小于70达因/厘米的涂层沉积在膜上以形成涂膜。 涂膜的RMS表面粗糙度为25nm至500nm，膜覆盖率为25％至60％，表面能小于70达因/厘米; 耐久性为10至5000微瓦。 根据使用薄膜的具体环境，可以优选10至500微瓦的耐久性。 膜的厚度为膜的RMS表面粗糙度的3〜100倍是优选的。

公开(公告)号：US20110293851A1

公开(公告)日：2011-12-01

申请号：US13147424

申请日：2006-02-02

Applicant: Roger Bollström ,  Anni Määttänen ,  Petri Ihalainen ,  Martti Toivakka ,  Jouko Peltonen

Inventor： Roger Bollström ,  Anni Määttänen ,  Petri Ihalainen ,  Martti Toivakka ,  Jouko Peltonen

IPC: B32B21/04 ,  B05D5/00 ,  B05D5/12 ,  B32B29/00 ,  B05D3/06 ,  B05D7/06 ,  B05D3/12 ,  B05D1/30 ,  B05D1/38 ,  B05D3/00

CPC classification number: H01L51/0097 ,  B41M5/5218 ,  B41M2205/38 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/052 ,  H01L51/0541 ,  H05K1/0366 ,  H05K1/0386 ,  H05K2201/0209 ,  H05K2201/0284 ,  Y02E10/549 ,  Y10T428/31971 ,  Y10T428/31989

Abstract: The invention relates to a method for creating a substrate for printed or coated functionality. The method comprises obtaining a base web substrate comprising cellulose and/or wood fibres, coating the base web substrate with a barrier layer, and coating the barrier layer with a top coat layer comprising mineral and/or pigment particles. The invention relates also to a substrate for printed or coated functionality, comprising a base web substrate layer comprising cellulose and/or wood fibres, a barrier layer, coated on the base web substrate layer, and a top coat layer comprising mineral and/or pigment particles, coated on the barrier layer. The invention relates also to a functional device and its use.

Abstract translation: 本发明涉及一种用于制造用于印刷或涂布功能的基材的方法。 该方法包括获得包含纤维素和/或木纤维的基底纤维网基材，用阻挡层涂覆基底纤维网基材，并用包含矿物和/或颜料颗粒的顶涂层涂覆阻挡层。 本发明还涉及一种用于印刷或涂布的功能性的基材，其包括基材纤维网基材层，其包含纤维素和/或木纤维，涂覆在基材纤维网基材层上的阻挡层和包含矿物和/或颜料的面漆层 颗粒，涂在阻挡层上。 本发明还涉及一种功能装置及其用途。

公开(公告)号：US20110252640A1

公开(公告)日：2011-10-20

申请号：US13166861

申请日：2011-06-23

Applicant: Michimasa Takahashi ,  Masakazu Aoyama

Inventor： Michimasa Takahashi ,  Masakazu Aoyama

IPC: H01K3/10

CPC classification number: H05K3/4691 ,  H05K1/0373 ,  H05K3/0032 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09536 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A method of manufacturing a wiring board including forming a base substrate, forming a first insulation layer on a first surface of the base substrate and a second insulating layer on a second surface of the substrate opposing the first surface, forming an IVH (Interstitial Via Hole) that penetrates the base substrate, and cutting the first insulating layer in a first area and cutting the second insulating layer in a second area offset from said first area to form a first substrate laminated to a second substrate with the base layer interposed therebetween, the second substrate having a smaller mounting area than that of the first substrate such that the first substrate extends beyond an edge of the second substrate.

Abstract translation: 一种制造布线板的方法，包括形成基底基板，在基底基板的第一表面上形成第一绝缘层，在与第一表面相对的第二表面上形成第二绝缘层，形成IVH（间隙通孔 ），其在第一区域中切割第一绝缘层，并且在与所述第一区域偏移的第二区域中切割第二绝缘层，以形成层压到第二基板上的第一基板，其中介于基板之间。 第二基板具有比第一基板的安装面积小的安装面积，使得第一基板延伸超过第二基板的边缘。

公开(公告)号：US08040685B2

公开(公告)日：2011-10-18

申请号：US12146032

申请日：2008-06-25

Applicant: Michimasa Takahashi ,  Masakazu Aoyama

Inventor： Michimasa Takahashi ,  Masakazu Aoyama

IPC: H05K1/11

CPC classification number: H05K3/4691 ,  H05K1/0366 ,  H05K3/0052 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/091 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/1536

Abstract: A wiring board and method of forming the wiring board. The wiring board includes a first substrate, and a second substrate having a smaller mounting area than a mounting area of the first substrate. A base substrate is laminated between the first substrate and the second substrate such that the first substrate extends beyond an edge of the second substrate, and at least one via formed in at least one of the first substrate or the second substrate. A thickness of a portion of the base substrate that is sandwiched between the first substrate and the second substrate is greater than a thickness of a portion of the base substrate that is not sandwiched between the first substrate and the second substrate.

Abstract translation: 布线基板及布线基板的形成方法。 布线板包括第一基板和具有比第一基板的安装面积小的安装面积的第二基板。 基底衬底层压在第一衬底和第二衬底之间，使得第一衬底延伸超过第二衬底的边缘，以及形成在第一衬底或第二衬底中的至少一个衬底中的至少一个通孔。 夹在第一基板和第二基板之间的基底基板的一部分的厚度大于未被夹在第一基板和第二基板之间的基底部分的厚度。

公开(公告)号：US08040676B2

公开(公告)日：2011-10-18

申请号：US12293151

申请日：2007-03-22

Applicant: Claus Peter Kluge

Inventor： Claus Peter Kluge

IPC: H05K7/20

CPC classification number: F21V29/70 ,  F21K9/23 ,  F21V29/71 ,  F21V29/713 ,  F21V29/75 ,  F21V29/763 ,  F21V29/86 ,  F21V29/89 ,  F21Y2105/10 ,  F21Y2115/10 ,  F28F2215/10 ,  H01L23/15 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3731 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/552 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L25/16 ,  H01L25/162 ,  H01L33/642 ,  H01L33/648 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H05K1/0203 ,  H05K1/0284 ,  H05K1/0306 ,  H05K1/0373 ,  H05K2201/0209 ,  H05K2201/09045 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00011

Abstract: A carrier body for electrical or electronic component elements or circuits, the carrier body being electrically nonconductive or virtually nonconductive. In order to simplify the carrier body while at the same time providing extremely improved heat dissipation, the invention process that the carrier body is provided integrally with heat-dissipating or heat-supplying cooling elements.

Abstract translation: 用于电气或电子部件元件或电路的载体主体，该载体主体是非导电的或几乎不导电的。 为了简化承载体，同时提供极大改善的散热，本发明的方法是将载体主体与散热或供热的冷却元件一体地设置。

公开(公告)号：US20110247873A1

公开(公告)日：2011-10-13

申请号：US13166570

申请日：2011-06-22

Applicant: Itsuo WATANABE ,  Kenzo Takemura ,  Akira Nagai ,  Kazuhiro Isaka ,  Osamu Watanabe ,  Kazuyoshi Kojima

Inventor： Itsuo WATANABE ,  Kenzo Takemura ,  Akira Nagai ,  Kazuhiro Isaka ,  Osamu Watanabe ,  Kazuyoshi Kojima

IPC: H05K1/11 ,  H05K13/04 ,  B32B37/14 ,  B32B37/10 ,  B32B37/12

CPC classification number: H01L24/83 ,  C09J9/02 ,  H01L23/49883 ,  H01L24/29 ,  H01L24/90 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/83851 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0271 ,  H05K3/323 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/0379 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T156/10 ,  Y10T156/109 ,  Y10T428/24942 ,  Y10T428/24959 ,  Y10T428/2852 ,  Y10T428/31511 ,  Y10T428/31515 ,  Y10T428/31855 ,  H01L2924/00

Abstract: An adhesive for bonding and securing a semiconductor chip to a circuit board and electrically connecting the electrodes of the two, and containing an adhesive resin composition and an inorganic filler being contained in an amount of 10 to 200 parts by weight of 100 parts by weight of the adhesive resin composition.

公开(公告)号：US08030579B2

公开(公告)日：2011-10-04

申请号：US12099957

申请日：2008-04-09

Applicant: Yukihiko Toyoda ,  Yoichiro Kawamura ,  Tomoyuki Ikeda

Inventor： Yukihiko Toyoda ,  Yoichiro Kawamura ,  Tomoyuki Ikeda

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/116 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/068 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09745 ,  H01L2924/00

Abstract: An object of the present invention is to provide a multilayered printed circuit board having a short wiring distance of the conductor circuits, wide option of the design of the conductor circuits and additionally excellent in reliability since cracking scarcely takes place in the interlaminar resin insulating layers in the vicinity of via-holes. The present invention is a multilayered printed circuit board comprising: a conductor circuit and an interlaminar resin insulating layer serially formed on a substrate in alternate fashion and in repetition, wherein a connection of the conductor circuits through the interlaminar resin insulating layers is performed by a via-hole, wherein via-holes in different level layers among the via-holes are formed so as to form a stack-via structure, and wherein at least one of the land diameters of the above-mentioned via-holes in different level layers having the stack via structure is different from the land diameters of other via-holes.

Abstract translation: 本发明的目的是提供一种具有导体电路的布线距离短的多层印刷电路板，可广泛选择导体电路的设计，并且由于在层间树脂绝缘层中几乎不发生破裂 通孔附近。 本发明是一种多层印刷电路板，包括：导体电路和层间树脂绝缘层，其以交替的方式和重复地串联形成在基板上，其中通过层间树脂绝缘层的导体电路的连接通过通孔 孔，其中形成通孔中的不同级别的通孔，以形成堆叠通孔结构，并且其中不同层级中的上述通孔的平台直径中的至少一个具有 堆叠通孔结构不同于其它通孔的焊盘直径。

公开(公告)号：US08021748B2

公开(公告)日：2011-09-20

申请号：US10557206

申请日：2004-09-29

Applicant: Motoo Asai ,  Kouta Noda ,  Yasushi Inagaki

Inventor： Motoo Asai ,  Kouta Noda ,  Yasushi Inagaki

IPC: B32B5/16

CPC classification number: H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K3/005 ,  H05K3/045 ,  H05K3/107 ,  H05K3/381 ,  H05K3/4602 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0245 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/1152 ,  H05K2203/1189 ,  Y10T428/25 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A printed wiring board is provided which includes an interlayer dielectric layer formed on a substrate from a curable resin having flaky particles dispersed therein. The printed wiring board is excellent in cooling/heating cycle resistance and packaging reliability while maintaining a satisfactory heat resistance, electrical insulation, heat liberation, connection reliability and chemical stability. Also a method of producing a printed wiring board is proposed in which an imprint method using a mold having formed thereon convexities corresponding to wiring patterns and viaholes to be formed being buried in an interlayer dielectric layer is used to form the wiring patterns and viaholes by transcribing the concavities of the mold to the interlayer dielectric layer. The imprint method permits to form the wiring patterns and viaholes but assures an easy and accurate transcription without any optical transcription or complicated etching. Thus, a multilayer printed wiring board excellent in insulation reliability and interlayer connection and having fine wiring patterns formed therein can be mass-produced extremely easily and inexpensively.

Abstract translation: 提供一种印刷电路板，其包括由分散在其中的片状颗粒的可固化树脂形成在基板上的层间电介质层。 印刷电路板在保持耐热性，电绝缘性，热释放性，连接可靠性和化学稳定性方面保持良好的冷/热循环阻力和包装可靠性。 还提出了一种制造印刷电路板的方法，其中使用在其中形成有对应于要形成的布线图案和通孔的凸起的模具被埋在层间电介质层中的模具的压印方法用于通过转录形成布线图案和通孔 模具与层间电介质层的凹部。 压印方法允许形成布线图案和通孔，但确保容易且准确的转录，无需任何光学转录或复杂蚀刻。 因此，绝缘可靠性和层间连接性优异，并且在其中形成的精细布线图案的多层印刷线路板可以极其容易且廉价地批量生产。

公开(公告)号：US08017715B2

公开(公告)日：2011-09-13

申请号：US12524214

申请日：2008-01-18

Applicant: Eiji Kinoshita ,  Tomoyuki Kishino ,  Kazuteru Kohno ,  Tatsuya Ogawa

Inventor： Eiji Kinoshita ,  Tomoyuki Kishino ,  Kazuteru Kohno ,  Tatsuya Ogawa

IPC: C08G63/02 ,  C08G64/00

CPC classification number: G11B5/73 ,  C08G63/187 ,  C08G63/672 ,  C08J5/18 ,  C08J2367/02 ,  C08L25/06 ,  C08L67/02 ,  C08L83/04 ,  H05K1/0373 ,  H05K1/0393 ,  H05K2201/0145 ,  H05K2201/0209 ,  Y10T428/31504 ,  Y10T428/31507 ,  C08L2666/02

Abstract: An object of the present invention is to provide a polyester film having excellent dimensional stability to temperature and humidity.The present invention is a polyester containing a dicarboxylic acid component and a diol component, wherein (i) the dicarboxylic acid component contains not less than 5 mol % and less than 50 mol % of a recurring unit represented by the following formula (A) and more than 50 mol % and not more than 95 mol % of a recurring unit represented by the following formula (B): wherein RA is an alkylene group having 2 to 10 carbon atoms, wherein RB is a phenylene group or naphthalenediyl group; and (ii) the diol component contains 90 to 100 mol % of a recurring unit represented by the following formula (C): —O—RC—O—  (C) wherein RC is an alkylene group having 2 to 10 carbon atoms, and a film comprising the same.

Abstract translation: 本发明的目的是提供一种对温度和湿度具有优异的尺寸稳定性的聚酯薄膜。 本发明是含有二羧酸成分和二醇成分的聚酯，其中（i）二羧酸成分含有下述通式（A）表示的重复单元的5摩尔％以上且50摩尔％以下，和 由下式（B）表示的重复单元大于50mol％且不大于95mol％：其中RA为碳原子数2〜10的亚烷基，RB为亚苯基或萘二甲基; 和（ii）二醇组分含有90至100摩尔％的由下式（C）表示的重复单元：-O-RC-O-（C）其中RC是具​​有2至10个碳原子的亚烷基，和 包含该膜的膜。

公开(公告)号：US20110204506A1

公开(公告)日：2011-08-25

申请号：US13099145

申请日：2011-05-02

Applicant: Siva Prakash GURRUM ,  Paul Joseph HUNDT ,  Vikas GUPTA

Inventor： Siva Prakash GURRUM ,  Paul Joseph HUNDT ,  Vikas GUPTA

IPC: H01L23/02

CPC classification number: H01L23/3737 ,  H01L23/293 ,  H01L23/373 ,  H01L23/433 ,  H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48472 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K1/0203 ,  H05K3/305 ,  H05K2201/0209 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic package 100 comprising a semiconductor device 105, a heat spreader layer 110, and a thermal interface material layer 115 located between the semiconductor device and the heat spreader layer. The thermal interface material layer includes a resin layer 120 having heat conductive particles 125 suspended therein. A portion of the particles are exposed on at least one non-planar surface 135 of the resin layer such that the portion of exposed particles 130 occupies a majority of a total area of a horizontal plane 140 of the non-planar surface.

Abstract translation: 包括位于半导体器件和散热器层之间的半导体器件105，散热层110和热界面材料层115的电子封装100。 热界面材料层包括其中悬置有导热颗粒125的树脂层120。 一部分颗粒暴露在树脂层的至少一个非平面表面135上，使得暴露的颗粒130的一部分占据非平面表面的水平面140的总面积的大部分。