公开(公告)号：US07427557B2

公开(公告)日：2008-09-23

申请号：US11075474

申请日：2005-03-09

Applicant: Glenn A. Rinne ,  J. Daniel Mis

Inventor： Glenn A. Rinne ,  J. Daniel Mis

IPC: H01L21/44

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05178 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05557 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/062 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2203/054 ,  H05K2203/0723 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Forming an electronic structure may include forming a seed layer on a substrate, and forming a mask on the seed layer. The mask may include an aperture therein exposing a portion of the seed layer, and a barrier layer may be formed on the exposed portion of the seed layer. A bump may be formed on the barrier layer, and the mask may be removed. In addition, portions of the seed layer may be selectively removed using the barrier layer as an etch mask.

Abstract translation: 形成电子结构可以包括在基底上形成种子层，并在种子层上形成掩模。 掩模可以包括其中露出种子层的一部分的孔，并且阻挡层可以形成在种子层的暴露部分上。 可以在阻挡层上形成凸起，并且可以去除掩模。 此外，可以使用阻挡层作为蚀刻掩模来选择性地去除种子层的部分。

公开(公告)号：US07416687B2

公开(公告)日：2008-08-26

申请号：US11693779

申请日：2007-03-30

Applicant: Tsutomu Uchimi ,  Masayuki Nagashima ,  Masaru Kobayashi ,  Hiroyuki Shirogane

Inventor： Tsutomu Uchimi ,  Masayuki Nagashima ,  Masaru Kobayashi ,  Hiroyuki Shirogane

IPC: H01B1/22 ,  H05K3/12

CPC classification number: H05K1/095 ,  H05K3/4069 ,  H05K3/4614 ,  H05K2201/0367

Abstract: There is provided an electroconductive paste composition that can form a coating film having satisfactory thickness by single coating work. The electroconductive paste composition can form bumps having satisfactory height even by a smaller number of times of coating than that in the prior art technique. The electroconductive paste composition comprises a phenolic resin, a melamine resin, an electroconductive powder, a solvent, and a bump forming aid comprising a monohydric alcohol having a terminal methoxy group and having at least one ether bond. The electroconductive paste composition can be used in a printed wiring board.

Abstract translation: 提供一种导电浆料组合物，其可以通过单次涂覆工作形成具有令人满意的厚度的涂膜。 导电糊组合物可以形成具有令人满意的高度的凸起，即使是比现有技术中的涂层次数少的次数也是如此。 导电糊组合物包含酚醛树脂，三聚氰胺树脂，导电粉末，溶剂和包含具有末端甲氧基并具有至少一个醚键的一元醇的凸块形成助剂。 导电糊剂组合物可用于印刷线路板。

公开(公告)号：US20080176416A1

公开(公告)日：2008-07-24

申请号：US11865327

申请日：2007-10-01

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01R12/00

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

公开(公告)号：US07402052B2

公开(公告)日：2008-07-22

申请号：US11865305

申请日：2007-10-01

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01R12/00

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

公开(公告)号：US20080164053A1

公开(公告)日：2008-07-10

申请号：US11971928

申请日：2008-01-10

Applicant: Daigo Matsubara ,  Osamu Chikagawa

Inventor： Daigo Matsubara ,  Osamu Chikagawa

IPC: H05K1/03 ,  H05K3/46

CPC classification number: H05K3/4007 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2201/0979 ,  H05K2203/308 ,  Y10T29/49163 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A ceramic electronic component achieves a sufficient drop resistance strength even when terminal electrodes are formed with a higher density. The ceramic electronic component includes a ceramic laminate including ceramic laminates which are laminated to each other, first terminal electrodes disposed in a peripheral portion of a bottom surface of the ceramic laminate, catch pad electrodes arranged in the ceramic laminate so as to face the respective first terminal electrodes, and sets each including at least two first via hole conductors, which electrically connect the first terminal electrodes and the respective catch pad electrodes.

Abstract translation: 陶瓷电子元件即使在以更高的密度形成端子电极时也能够获得足够的降阻强度。 陶瓷电子部件包括层叠陶瓷层叠体的陶瓷层叠体，设置在陶瓷层叠体的底面的周边部的第一端子电极，配置在陶瓷层叠体中的捕捉垫电极，以与第一 端子电极和每个包括至少两个第一通孔导体的组件，其将第一端子电极和相应的焊盘电极电连接。

公开(公告)号：US20080150135A1

公开(公告)日：2008-06-26

申请号：US11850767

申请日：2007-09-06

Applicant: Yukifumi Oyama ,  Hidetoshi Nishiwaki ,  Toshihiko Nishio ,  Kazushige Toriyama ,  Yasumitsu Orii

Inventor： Yukifumi Oyama ,  Hidetoshi Nishiwaki ,  Toshihiko Nishio ,  Kazushige Toriyama ,  Yasumitsu Orii

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L24/13 ,  B23K1/0016 ,  B23K3/0623 ,  B23K2101/40 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/4985 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/7515 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3511 ,  H05K3/3478 ,  H05K2201/0367 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/041 ,  H05K2203/049 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for mounting a semiconductor part on a circuit substrate is provided, which includes preparing the semiconductor part having a surface thereof provided with a plurality of stud-bumps, preparing a solder substrate having a surface thereof on which solid-solders corresponding to respective ones of the plurality of stud-bumps are arranged, preparing the circuit substrate having a surface thereof provided with connecting pads corresponding to respective ones of the plurality of stud-bumps, attaching the corresponding solid-solders on the solder substrate to respective tip ends of the plurality of stud bumps, separating the solid-solders attached to the tip ends of the stud-bumps from the solder substrate, contacting the solid-solder attached to respective ones of the tip ends of the stud-bumps with the corresponding connecting pads, and heating the solid-solders contacted with the corresponding connecting pads thereby establishing solder connection between respective ones of the stud-bumps and the corresponding connecting pads.

Abstract translation: 提供了一种在电路基板上安装半导体部件的方法，其包括制备其表面设置有多个凸起凸块的半导体部件，制备其表面上的固体焊料对应于其的表面的焊料基板 布置多个柱状突起的准备电路基板，其表面设置有与多个突起凸块中的各个凸起对应的连接焊盘，将相应的固体焊料附着在焊料基板上， 多个柱形凸块，将附接到凸起凸点的末端的固体焊料与焊料基板分离，使与柱连接凸块的相应顶端的固体焊料与相应的连接焊盘接触，以及 加热与相应的连接焊盘接触的固体焊料，从而在各自的焊料之间建立焊接连接 凹凸和相应的连接垫。

公开(公告)号：US20080135283A1

公开(公告)日：2008-06-12

申请号：US11883801

申请日：2006-04-14

Applicant: Kunio Hibino ,  Yoshihiro Tomura ,  Yoshihiko Yagi ,  Kazuhiro Nishikawa

Inventor： Kunio Hibino ,  Yoshihiro Tomura ,  Yoshihiko Yagi ,  Kazuhiro Nishikawa

IPC: H05K3/30 ,  H01B5/00 ,  H05K1/18 ,  B29C39/10

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/11901 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13113 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/207 ,  H05K3/245 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2203/0113 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A protruding electrodes is formed on a lead electrode of an electronic component, and the protruding electrodes comprises a first conductor formed on the lead electrode of the electronic component, and a second conductor overlaid on the first conductor by using a transfer mold having a concavity. By virtue of this structure, protruding electrodes of any configuration can be formed in fine pitches.

Abstract translation: 在电子部件的引线电极上形成突起电极，突出电极包括形成在电子部件的引线电极上的第一导体和通过使用具有凹度的转移模具覆盖在第一导体上的第二导体。 通过这种结构，可以以细间距形成任何构造的突出电极。

公开(公告)号：US07382049B2

公开(公告)日：2008-06-03

申请号：US11313435

申请日：2005-12-19

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/563 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13019 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73203 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/381 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/0379 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A chip package includes a chip, a carrier, and at least a bump connecting structure for connecting the chip to the carrier. The bump connecting structure includes a first metal bump disposed on a chip pad of the chip and has a first height relative to a passivation layer of the chip, a second metal bump disposed on a carrier pad of the carrier and has a second height relative to a solder mask layer of the carrier, and a middle metal part disposed between the first and the second metal bumps. The sum of the minimum distance between the first and the second metal bumps, the first height of the first metal bump, and the second height of the second metal bump is less than 60 micrometers. The melting point of the middle metal part is lower than that of the first and the second metal bumps.

Abstract translation: 芯片封装包括芯片，载体和用于将芯片连接到载体的至少一个凸块连接结构。 凸块连接结构包括设置在芯片的芯片焊盘上并具有相对于芯片的钝化层的第一高度的第一金属凸块，设置在载体的载体焊盘上的第二金属凸块，并且具有相对于 载体的焊接掩模层，以及设置在第一和第二金属凸块之间的中间金属部件。 第一和第二金属凸块之间的最小距离，第一金属凸块的第一高度和第二金属凸块的第二高度之和小于60微米。 中间金属部分的熔点低于第一和第二金属凸块的熔点。

公开(公告)号：US07380338B2

公开(公告)日：2008-06-03

申请号：US11158044

申请日：2005-06-22

Applicant: Yu-Tuan Lee

Inventor： Yu-Tuan Lee

IPC: H05K3/02 ,  H05K3/12 ,  H01R9/00 ,  H01R3/00

CPC classification number: H05K3/4007 ,  H05K1/0306 ,  H05K3/386 ,  H05K3/4644 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0367 ,  H05K2201/09909 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49158

Abstract: A circuit board includes a substrate, an insulating layer, at least one protrusion, and a first circuit layer. The insulating layer is disposed on the substrate and has at least one protrusion-positioning region. At least a part of the protrusion is disposed on the protrusion-positioning region. The first circuit layer is disposed on the insulating layer and has at least one trace line extending onto the protrusion.

Abstract translation: 电路板包括基板，绝缘层，至少一个突起和第一电路层。 绝缘层设置在基板上并且具有至少一个突出定位区域。 突起的至少一部分设置在突起定位区域上。 第一电路层设置在绝缘层上并且具有延伸到突起上的至少一条迹线。

公开(公告)号：US07371973B1

公开(公告)日：2008-05-13

申请号：US09830635

申请日：1999-03-04

Applicant: Alexandr Ivanovich Taran

Inventor： Alexandr Ivanovich Taran

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/363 ,  H01L23/5384 ,  H01L24/80 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/8203 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01039 ,  H01L2924/01041 ,  H01L2924/01058 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/3447 ,  H05K3/368 ,  H05K3/4007 ,  H05K3/4647 ,  H05K2201/0367 ,  H05K2201/09827 ,  H05K2201/10303 ,  H05K2201/10666 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The contact node comprises at least two metallized contacts coupled with conductive paths arranged on surfaces of connection layers made on the base of a dielectric material and mutually aligned and interconnected electrically and mechanically by conductive binding material. The contact node is a joint between a contact made in the form of a metallized pad coupled with a conductive path on the surface of the underlying connection layer and a respective contact made in the form of a metallized hole in a dielectric material layer.

Abstract translation: 接触节点包括至少两个金属化触点，其与布置在电介质材料的基底上形成的连接层的表面上的导电通路耦合，并且通过导电结合材料电和机械地相互对准和互连。 接触节点是在金属化焊盘形式的接触件之间的接头，其与下层连接层的表面上的导电路径耦合，以及在电介质材料层中以金属化孔的形式制成的相应触点。