公开(公告)号：US20080290512A1

公开(公告)日：2008-11-27

申请号：US12125421

申请日：2008-05-22

Applicant: Masayuki UCHIDA ,  Hisashi ITO ,  Kazuhito HIGUCHI ,  Takashi TOGASAKI

Inventor： Masayuki UCHIDA ,  Hisashi ITO ,  Kazuhito HIGUCHI ,  Takashi TOGASAKI

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H05K3/3436 ,  H01L21/563 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16013 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81211 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/3463 ,  H05K3/3494 ,  H05K2201/0379 ,  H05K2201/09427 ,  H05K2203/1121 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: For a suppressed breakage after a flip chip connection of a semiconductor device using a low-permittivity insulation film and a lead-free solder together, with an enhanced production yield, bump electrodes (2) are heated by a temperature profile having, after a heating up to a melting point of the bump electrodes (2) or more, a cooling in which a temperature within a range of 190 to 210° C. is kept for an interval of time within a range of 3 to 15 minutes, and a condition is met, such that 1.4

Abstract translation: 为了在使用低介电常数绝缘膜和无铅焊料的半导体器件的倒装芯片连接之后抑制破坏，以提高的生产成本，凸起电极（2）被加热了在加热之后的温度分布 直到凸起电极（2）的熔点以上，将在190〜210℃的范围内的温度保持在3〜15分钟的范围内的时间间隔的冷却，以及条件 使得1.4

公开(公告)号：US20080264676A1

公开(公告)日：2008-10-30

申请号：US11976207

申请日：2007-10-22

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: H05K1/00

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

Abstract translation: 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

公开(公告)号：US20080251896A1

公开(公告)日：2008-10-16

申请号：US12157804

申请日：2008-06-12

Applicant: Tony Dambrauskas

Inventor： Tony Dambrauskas

IPC: H01L23/498

CPC classification number: H01L21/743 ,  H01L23/535 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K2201/0379 ,  H05K2201/09809 ,  H05K2203/0369 ,  H01L2924/00

Abstract: A method of manufacturing a coaxial trace (100) within a surrounding material (190) includes: providing a first substrate (191, 410) and a second substrate (192, 1010) composed of the surrounding material; forming a first portion (101, 601) of the coaxial trace in the first substrate; forming a second portion (102, 1001) of the coaxial trace in the second substrate; aligning the first portion of the coaxial trace with the second portion of the coaxial trace; and bonding the first portion of the coaxial trace to the second portion of the coaxial trace.

Abstract translation: 在周围材料（190）内制造同轴线迹（100）的方法包括：提供由周围材料构成的第一衬底（191,410）和第二衬底（192,1010）; 在所述第一基板中形成所述同轴线迹的第一部分（101,601）; 在所述第二基板中形成所述同轴线迹的第二部分（102,1001） 将同轴线迹的第一部分与同轴线迹的第二部分对准; 以及将所述同轴线迹的第一部分接合到所述同轴线迹的第二部分。

公开(公告)号：US07417196B2

公开(公告)日：2008-08-26

申请号：US11684147

申请日：2007-03-09

Applicant: Ryuichiro Wada ,  Tetsuya Ikeda

Inventor： Ryuichiro Wada ,  Tetsuya Ikeda

IPC: H05K1/16

CPC classification number: H05K1/186 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/023 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/183 ,  H05K3/4614 ,  H05K3/4629 ,  H05K2201/0379 ,  H05K2201/091 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A chip-type electronic component built-in multilayer board includes a multilayer board including two or more layered dielectric layers and an inner conductor pattern, and a chip-type electronic component which is provided at the interface of the upper and lower dielectric layers and includes an external terminal electrode. The external terminal electrode is connected to an in-plane conductor provided at a interface via a first connection conductor extending along the chip-type electronic component in the lower direction from the interface of the upper and lower dielectric layers, and a second connection conductor extending along the chip-type electronic component in the upper direction from the interface of the upper and lower dielectric layers.

Abstract translation: 芯片型电子元件内置多层板包括：多层基板，包括两层或多层叠层电介质层和内导体图案;以及芯片型电子元件，其设置在上下电介质层的界面处，并包括 外部端子电极。 外部端子电极通过第一连接导体连接到设置在界面处的面内导体，所述第一连接导体沿着所述芯片型电子部件从所述上部和下部电介质层的界面向下方延伸;以及第二连接导体， 沿着芯片型电子部件从上下电介质层的界面向上方延伸。

公开(公告)号：US20080185717A1

公开(公告)日：2008-08-07

申请号：US12027280

申请日：2008-02-07

Applicant: Dai SASAKI

Inventor： Dai SASAKI

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H05K3/323 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/28 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/78301 ,  H01L2224/81903 ,  H01L2224/83193 ,  H01L2224/83851 ,  H01L2224/83885 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0781 ,  H01L2924/351 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/10674 ,  H05K2203/0278 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device includes a semiconductor chip mounted on a printed circuit board with a chip electrode being coupled to a board electrode via a bump electrode. An insulating resin layer including therein conductive particles is interposed between the bump electrode and each of the chip electrode and board electrode. The conductive particles couple together the bump electrode and the each of the chip electrode and the board electrode. The conductive particles and the bump electrode are deformed to have a flat shape due the stress applied between the semiconductor chip and the printed circuit board.

Abstract translation: 半导体器件包括安装在印刷电路板上的半导体芯片，其中芯片电极通过凸块电极耦合到板电极。 包括导电粒子的绝缘树脂层插入在凸块电极与芯片电极和板电极之间。 导电颗粒将突起电极和芯片电极和板电极中的每一个耦合在一起。 由于在半导体芯片和印刷电路板之间施加的应力，导电粒子和凸起电极变形为具有平坦的形状。

公开(公告)号：US07400222B2

公开(公告)日：2008-07-15

申请号：US10864077

申请日：2004-06-08

Applicant: Young Se Kwon ,  Ju Hyun Ko ,  Seong Ho Shin

Inventor： Young Se Kwon ,  Ju Hyun Ko ,  Seong Ho Shin

IPC: H01P3/06

CPC classification number: H05K1/0221 ,  H01P3/06 ,  H01P11/005 ,  H05K1/0272 ,  H05K3/4614 ,  H05K2201/0379 ,  H05K2201/09809 ,  H05K2201/09981

Abstract: Disclosed herein are a transmission line of coaxial type and a manufacturing method thereof, capable of preventing a radiative signal loss of signal lines during transmission of an RF signal and removing signal interference between adjacent signal lines, thus allowing signal lines to be compactly arrayed during a manufacture of IC, and reducing a dimension of the IC. The transmission line of coaxial type includes grooves provided on a semiconductor substrate, a first ground layer, an electrically conductive epoxy coated on a flat part of the first ground layer except the grooves, second ground layers provided on the electrically conductive epoxy, a dielectric film provided at a position above the grooves and the second ground layers, a third ground layer provided on an upper surface of the dielectric film, and signal lines placed in spaces defined by the grooves and a lower surface of the dielectric film. In this case, the electrically conductive epoxy is coated on only contact surfaces of the first and second ground layers, and the signal lines are attached to the lower surface of the dielectric film.

Abstract translation: 这里公开了一种同轴型传输线及其制造方法，其能够防止RF信号传输期间的信号线的辐射信号损失并消除相邻信号线之间的信号干扰，从而允许信号线在 制造IC，并减小IC的尺寸。 同轴型传输线包括设置在半导体衬底上的沟槽，第一接地层，涂覆在第一接地层的除了槽之外的平坦部分上的导电环氧树脂，设置在导电环氧树脂上的第二接地层，介电膜 设置在沟槽和第二接地层上方的位置，设置在电介质膜的上表面上的第三接地层和放置在由沟槽和电介质膜的下表面限定的空间中的信号线。 在这种情况下，仅在第一和第二接地层的接触表面上涂覆导电环氧树脂，并且信号线附着到电介质膜的下表面。

公开(公告)号：US07378297B2

公开(公告)日：2008-05-27

申请号：US11441794

申请日：2006-05-26

Applicant: Eric Beyne

Inventor： Eric Beyne

IPC: H01L21/00 ,  H01L23/48 ,  H01L31/02

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/563 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/11005 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/9211 ,  H01L2224/92125 ,  H01L2224/92222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/1433 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2924/00012

Abstract: A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder ball. The first and second elements are bonded by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a first layer of non-conductive material and the second solder ball is laterally embedded in a second layer of non-conductive material, such that the upper part of the first solder ball and upper part of the second solder ball are not covered by the non-conductive material. A third solder volume is applied on one or both of the embedded first or second solder balls, prior to the bonding.

Abstract translation: 描述用于结合元件的装置和方法。 在第一元件的主表面上产生第一焊球。 在第二元件的主表面上产生第二焊球。 在第一焊球和第二焊球之间提供接触。 第一和第二元件通过施加回流作用而结合，由此焊球熔化并形成接合的焊球结构。 在接合之前，第一焊球侧向嵌入在第一非导电材料层中，并且第二焊球侧向嵌入第二非导电材料层中，使得第一焊球的上部和 第二焊球的上部不被非导电材料覆盖。 在接合之前，在嵌入的第一或第二焊球的一个或两个上施加第三焊料体积。

公开(公告)号：US20080014668A1

公开(公告)日：2008-01-17

申请号：US11862149

申请日：2007-09-26

Applicant: Gary Brist ,  Bryce Horine ,  Stephen Hall

Inventor： Gary Brist ,  Bryce Horine ,  Stephen Hall

IPC: H01L21/00

CPC classification number: H05K1/024 ,  H01P3/121 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/037 ,  H05K2201/0379 ,  H05K2201/09981

Abstract: In some embodiments a channel is formed by combining two imprinted subparts each made of printed circuit board material and the imprinted subparts are laminated to form a waveguide. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，通过组合由印刷电路板材料制成的两个压印的子部件形成通道，并且压印的子部件被层压以形成波导。 描述和要求保护其他实施例。

公开(公告)号：US20070154157A1

公开(公告)日：2007-07-05

申请号：US11322964

申请日：2005-12-30

Applicant: Bryce D. Horine ,  Gary A. Brist ,  Stephen H. Hall

Inventor： Bryce D. Horine ,  Gary A. Brist ,  Stephen H. Hall

IPC: G02B6/10

CPC classification number: H05K1/024 ,  H01P3/121 ,  H01P11/002 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/037 ,  H05K2201/0379 ,  H05K2201/09981 ,  Y10T156/1002

Abstract: In some embodiments a channel is formed in printed circuit board material, the formed channel is plated to form at least two side walls of a quasi-waveguide, and printed circuit board material is laminated to the plated channel using thermoset adhesive. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，通道形成在印刷电路板材料中，形成的通道被电镀以形成准波导的至少两个侧壁，并且使用热固性粘合剂将印刷电路板材料层压到电镀通道上。 描述和要求保护其他实施例。

公开(公告)号：US20070154156A1

公开(公告)日：2007-07-05

申请号：US11322488

申请日：2005-12-30

Applicant: Gary Brist ,  Bryce Horine ,  Stephen Hall

Inventor： Gary Brist ,  Bryce Horine ,  Stephen Hall

IPC: G02B6/10

CPC classification number: H05K1/024 ,  H01P3/121 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/037 ,  H05K2201/0379 ,  H05K2201/09981

Abstract: In some embodiments a channel is formed by combining two imprinted subparts each made of printed circuit board material and the imprinted subparts are laminated to form a waveguide. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，通过组合由印刷电路板材料制成的两个压印的子部件形成通道，并且将压印的子部件层压以形成波导。 描述和要求保护其他实施例。