公开(公告)号：US06967282B2

公开(公告)日：2005-11-22

申请号：US10794491

申请日：2004-03-05

Applicant: Samual D. Tonomura ,  Terry C. Cisco ,  Clinton O. Holter

Inventor： Samual D. Tonomura ,  Terry C. Cisco ,  Clinton O. Holter

IPC: H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K9/00

CPC classification number: H01L23/552 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81801 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/3025 ,  H01P1/2005 ,  H05K1/0236 ,  H05K1/0306 ,  H05K1/09 ,  H05K2201/0715 ,  H05K2201/09336 ,  H05K2201/09681 ,  H01L2924/00

Abstract: A hybrid assembly having improved cross talk characteristics includes a substrate having an upper surface. Conductive paths on the upper surface are provided for conducting high frequency signals. Regular polygons made of an electromagnetic band gap (EBG) material having slow wave characteristics are deposited on the upper surface and form a lattice for tessellating the upper surface. Each of the polygons has a periphery. The polygons are separated along their periphery from adjacent polygons by an interspace and are covered with an insulating material. Second polygons, also made of an electromagnetic band gap material, are deposited over the insulating material. Semiconductor structures are mounted over the second polygons. The semiconductor structures have a plurality of electrical contacts with the conductive paths. The regular polygons can be hexagons, triangles, octagons or any other combination that forms a lattice and can be printed onto the substrate.

Abstract translation: 具有改进的串扰特性的混合组件包括具有上表面的基板。 设置上表面的导电路径用于传导高频信号。 由具有慢波特性的电磁带隙（EBG）材料制成的常规多边形沉积在上表面上并形成用于镶嵌上表面的格子。 每个多边形都有一个周边。 多边形沿其周边与邻近的多边形间隔开并用绝缘材料覆盖。 也由电磁带隙材料制成的第二多边形沉积在绝缘材料上。 半导体结构安装在第二多边形上。 半导体结构具有多个与导电路径的电接触。 正多边形可以是六边形，三角形，八边形或形成网格并可以印刷到基底上的任何其他组合。

公开(公告)号：US06963034B2

公开(公告)日：2005-11-08

申请号：US10093482

申请日：2002-03-11

Applicant: Mizuki Iwanami

Inventor： Mizuki Iwanami

IPC: H05K1/02 ,  H01F17/00 ,  H05K1/00 ,  H05K1/16 ,  H05K3/46

CPC classification number: H01F17/0013 ,  H05K1/0298 ,  H05K1/165 ,  H05K3/4688 ,  H05K2201/086 ,  H05K2201/09336 ,  H05K2201/097

Abstract: An inductor device having plural spiral-shaped interconnection structures connected to each other and extending in plural power source layers, the power source layers being in different levels of a multilayer printed board. The printed board having first and second current loops. The loops share part of a common current path.

Abstract translation: 一种电感器件，具有多个螺旋形互连结构，彼此连接并在多个电源层中延伸，所述电源层处于多层印刷电路板的不同级别。 该印刷电路板具有第一和第二电流回路。 循环共享公共当前路径的一部分。

公开(公告)号：US20050235233A1

公开(公告)日：2005-10-20

申请号：US11160355

申请日：2005-06-21

Applicant: Jimmy Hsu

Inventor： Jimmy Hsu

IPC: H01L23/498 ,  H01L23/552 ,  H05K1/00 ,  H05K1/02 ,  G06F17/50 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L23/49838 ,  H01L23/552 ,  H01L2924/15173 ,  H05K1/0218 ,  H05K1/0298 ,  H05K2201/09336

Abstract: A multi-layered substrate has a voltage reference signal circuit layout therein. A major change in the design of the multi-layered substrate is the moving of a reference signal trace from a signal layer to a non-signaling layer. Once the reference signal trace is moved, the signal traces within the signal layer can have a larger layout area. Similarly, the reference signal trace within the non-signaling layer can have greater layout flexibility in addition to electromagnetic shielding from other signal traces. Moreover, the reference signal trace having a greater width may be used to reduce parasitic resistance within the reference signal circuit.

Abstract translation: 多层基板在其中具有电压参考信号电路布局。 多层基板的设计的主要变化是将参考信号迹线从信号层移动到非信号层。 一旦参考信号迹线被移动，信号层内的信号迹线就可以具有更大的布局面积。 类似地，除了来自其他信号迹线的电磁屏蔽之外，非信令层内的参考信号迹线可以具有更大的布局灵活性。 此外，具有较大宽度的参考信号迹线可用于减小参考信号电路内的寄生电阻。

公开(公告)号：US20050194169A1

公开(公告)日：2005-09-08

申请号：US10800173

申请日：2004-03-11

Applicant: Samuel Tonomura

Inventor： Samuel Tonomura

IPC: H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K9/00

CPC classification number: H01L23/552 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/81801 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/3025 ,  H01P1/2005 ,  H05K1/0236 ,  H05K1/0306 ,  H05K1/09 ,  H05K2201/0715 ,  H05K2201/09336 ,  H05K2201/09681 ,  H01L2924/00

Abstract: A hybrid assembly having improved cross talk characteristics includes an electromagnetic band gap (EBG) layer on a substrate having an upper surface and a lower surface and a semiconductor structure (MMIC) mounted above the EBG layer. A plurality of stars made of an EBG material are preferably printed, or deposited, on the upper surface. The EBG material has slow wave characteristics. The plurality of stars tessellates the upper surface between conductive paths. Each of the stars has a center section formed from a regular polygon, the center section having projections extending from the center section. The projections and the center section form a periphery. The periphery engages adjacent stars along the periphery. Stars are separated from adjacent stars by an interspace. Each of the stars is connected to a conductive via, in turn connected to ground potential. A conductive layer at ground potential is electrically continuous with vias used to interconnect all stars forming the EBG layer.

Abstract translation: 具有改进的串扰特性的混合组件包括在具有上表面和下表面的基底上的电磁带隙（EBG）层和安装在EBG层上方的半导体结构（MMIC）。 由EBG材料制成的多个恒星优选地印刷或沉积在上表面上。 EBG材料具有慢波特性。 多个星星细分导电路径之间的上表面。 每个恒星具有由正多边形形成的中心部分，中心部分具有从中心部分延伸的突起。 突起和中心部分形成外围。 周边沿周边与相邻的星星接合。 星星通过间隙与相邻星星分离。 每颗恒星连接到一个导电通孔，又连接到地电位。 接地电位的导电层与用于互连形成EBG层的所有恒星的通孔电连接。

公开(公告)号：US20050099240A1

公开(公告)日：2005-05-12

申请号：US10783596

申请日：2004-02-19

Applicant: Yu Lin ,  Shang Yeh

Inventor： Yu Lin ,  Shang Yeh

IPC: H01P3/02 ,  H05K1/00 ,  H05K1/02 ,  H01P3/04

CPC classification number: H05K1/0245 ,  H01P3/02 ,  H05K1/0219 ,  H05K1/0298 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09672 ,  H05K2201/09709

Abstract: An arrangement of differential pairs in a multi-layer printed circuit board is provided for eliminating crosstalk. The arrangement of differential pairs in the multi-layer printed circuit board includes a first differential pair, and a second differential pair. The first differential pair and the second differential pair may each be a driven pair or a victim pair. By properly arranging the first differential pair and the second differential pair, in accordance with the present invention, the resultant crosstalk on the first differential pair induced by the second differential pair, or vice versa, is substantially zero or negligible.

Abstract translation: 提供了一种用于消除串扰的多层印刷电路板中的差分对的布置。 多层印刷电路板中的差分对的布置包括第一差分对和第二差分对。 第一差分对和第二差分对可以各自为驱动对或受害对。 通过适当地布置第一差分对和第二差分对，根据本发明，由第二差分对引起的第一差分对上产生的串扰基本为零或可忽略。

公开(公告)号：US20050039947A1

公开(公告)日：2005-02-24

申请号：US10949290

申请日：2004-09-27

Applicant: Tohru Ohsaka

Inventor： Tohru Ohsaka

IPC: H05K1/02 ,  H05K3/46 ,  H05K7/06

CPC classification number: H05K1/0216 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09354

Abstract: A multi-layered printed wiring board is provided that is capable of securing required wiring density even with a decreased number of wiring layers and reducing radiation noises. The multi-layered printed wiring board has at least three wiring layers each at least having at least one power supply line or a ground line, and another kind of line, said wiring layers each having an outer edge. A ground line is formed at the outer edge of at least one of the wiring layers. A basic power supply line is formed inside the ground line. At least one power supply line extends from the basic power supply line. A plurality of electronic parts are mounted on at least one of the wiring layers. The at least one power supply line is wired to mounting positions of the electronic parts via at least one of the wiring layers.

Abstract translation: 提供了一种多层印刷电路板，即使在布线层数量减少并且减少辐射噪声的情况下也能够确保所需的配线密度。 多层印刷电路板具有至少三个布线层，每个布线层至少具有至少一个电源线或接地线，并且另一种线，所述布线层各自具有外边缘。 在至少一个布线层的外边缘处形成接地线。 在地线内形成基本电源线。 至少一条电源线从基本电源线延伸。 多个电子部件安装在至少一个布线层上。 所述至少一个电源线经由所述布线层中的至少一个布线到所述电子部件的安装位置。

公开(公告)号：US20040212971A1

公开(公告)日：2004-10-28

申请号：US10828307

申请日：2004-04-21

Applicant: FUJI XEROX CO., LTD.

Inventor： Daisuke Iguchi

IPC: H05K007/06

CPC classification number: H05K1/0251 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/12042 ,  H05K1/0222 ,  H05K1/0231 ,  H05K1/0245 ,  H05K1/115 ,  H05K1/162 ,  H05K3/3447 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/0949 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09809 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a printed circuit board of the invention, a first signal wiring layer, a first ground layer, a second ground layer and a second signal wiring layer are laminated via an insulating material. A first signal wiring is formed on the first signal wiring layer and a second signal wiring is formed on the second signal wiring layer. The two signal wirings are connected via a first through hole. The conductive first ground layer and the conductive second ground layer are connected via a second through hole. The second through hole is insulated from the first through hole and formed so as to surround the first through hole.

Abstract translation: 在本发明的印刷电路板中，通过绝缘材料层叠第一信号布线层，第一接地层，第二接地层和第二信号布线层。 第一信号布线形成在第一信号布线层上，第二信号布线形成在第二信号布线层上。 两个信号布线通过第一通孔连接。 导电第一接地层和导电第二接地层经由第二通孔连接。 第二通孔与第一通孔绝缘并形成为围绕第一通孔。

公开(公告)号：US20040006407A1

公开(公告)日：2004-01-08

申请号：US10330297

申请日：2002-12-30

Inventor： Chun Hung Chen ,  Hsiu Tzu Chen ,  Yen Chen Chen

IPC: G06F007/00

CPC classification number: H05K1/0262 ,  H05K1/0216 ,  H05K1/0298 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09663

Abstract: A layer allocating apparatus for a multi-layer circuit board is disclosed. In a preferred embodiment, the layer allocating apparatus arranged from top to bottom as a component layer, a ground layer, a power layer, and a solder layer. The powerlayer is sliced into a plurality of reference ground areas each is located at somewhere to correspond to signal layout areas of the solder layer, so as to allow signal lines of the component layer and solder layer to take reference to the reference ground areas on the adjacent power layer. The power layer also includes a plurality of power layers each provides different operating voltages, and electrically couples with corresponding power layouts of the solder layer and component layer through vias, thereby enlarging the total area of power planes, so as to provide a table power source and attenuate the ground/bounce effect.

Abstract translation: 公开了一种用于多层电路板的层分配装置。 在优选实施例中，作为组件层，从顶部到底部布置的层分配装置，接地层，功率层和焊料层。 功率层被切割成多个参考接地区域，每个参考接地区域位于与焊料层的信号布局区域相对应的某处，以便允许组件层和焊料层的信号线参考在焊接层​​上的参考接地区域 相邻功率层。 功率层还包括多个功率层，每个功率层各自提供不同的工作电压，并且通过通孔与焊料层和组件层的相应功率布局电耦合，从而扩大电源平面的总面积，从而提供工作台电源 并衰减地面/反弹效果。

公开(公告)号：US06573600B2

公开(公告)日：2003-06-03

申请号：US09817787

申请日：2001-03-27

Applicant: Atsushi Kikuchi ,  Makoto Iijima ,  Yoshihiko Ikemoto ,  Muneharu Morioka ,  Yoshiyuki Kimura

Inventor： Atsushi Kikuchi ,  Makoto Iijima ,  Yoshihiko Ikemoto ,  Muneharu Morioka ,  Yoshiyuki Kimura

IPC: G01R1900

CPC classification number: H05K1/0245 ,  H01L23/13 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K2201/09336 ,  H05K2201/09345 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A multilayer wiring substrate includes differential signal wires placed within a first insulating layer between a first power-supply plane and a first ground plane; and general signal wires placed within a second insulating layer between a second power-supply plane and a second ground plane. In the multilayer wiring substrate, the differential signal wires are placed in a different plane from a plane having each of the general signal wires so that the different plane includes a first area having the differential signal wires, and a second area having one of the second power-supply plane and the second ground plane. The general signal wires are placed in a vertical direction of the second area in a laminated state so that each of the general signal wires is placed between the second power-supply plane and the second ground plane.

Abstract translation: 多层布线基板包括布置在第一电源平面和第一接地平面之间的第一绝缘层内的差动信号线; 以及放置在第二电源平面和第二接地平面之间的第二绝缘层内的一般信号线。 在多层布线基板中，差分信号线被放置在与具有每个通用信号线的平面不同的平面中，使得不同的平面包括具有差分信号线的第一区域，以及具有第二 电源平面和第二个接地层。 通常的信号线以叠层状态放置在第二区域的垂直方向上，使得每条通用信号线都位于第二电源平面和第二接地面之间。

公开(公告)号：US20030034868A1

公开(公告)日：2003-02-20

申请号：US10217557

申请日：2002-08-13

Applicant: Alps Electric Co., Ltd.

Inventor： Shigeru Osada

IPC: H01F005/00

CPC classification number: H05K1/165 ,  H01F5/003 ,  H01F17/0033 ,  H05K3/222 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/097 ,  H05K2201/10636 ,  H05K2203/171 ,  Y02P70/611

Abstract: In a coupling adjusting structure for a double-tuned circuit according to the present invention, first and second coils are configured such that a pair of first conductive patterns formed on a first surface of a printed circuit and a corresponding pair of second conductive patterns formed on a second surface of the printed circuit board are connected via corresponding connecting conductors, thereby making the first and second coils low and thin. Also, one end of the first coil and the corresponding end of the second coil are disposed close to each other, a first ground conductive pattern is disposed at least on the first surface of the printed circuit, and a first jumper connected to the first ground conductive pattern is disposed between the first and second coils so as to adjust an inductive coupling of the double-tuned circuit, thereby achieving a coupling adjusting structure for a double-tuned circuit whose inductive coupling is adjustable.

Abstract translation: 在根据本发明的用于双调谐电路的耦合调整结构中，第一和第二线圈被配置成使得形成在印刷电路的第一表面上的一对第一导电图案和形成在 印刷电路板的第二表面经由相应的连接导体连接，从而使第一和第二线圈变薄和薄。 此外，第一线圈的一端和第二线圈的对应端部彼此靠近设置，第一接地导体图案至少设置在印刷电路的第一表面上，并且第一跳线连接到第一接地 导电图案设置在第一和第二线圈之间，以便调整双调谐电路的电感耦合，从而实现用于电感耦合可调节的双调谐电路的耦合调节结构。