公开(公告)号：US20150228571A1

公开(公告)日：2015-08-13

申请号：US14592105

申请日：2015-01-08

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Satoshi SHIRAKI

IPC: H01L23/498 ,  H05K1/02 ,  H01L23/04 ,  H05K1/11 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12044 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1533 ,  H01L2924/181 ,  H05K1/111 ,  H05K1/144 ,  H05K3/0052 ,  H05K3/0097 ,  H05K2201/0939 ,  H05K2201/09409 ,  H05K2201/09418 ,  H05K2201/10977 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: A wiring substrate includes a block with substrates laid out in an array. The block includes corners and a plan view center. Each substrate includes a substrate body. Pads are formed on the substrate body. Each pad includes a pad surface. The pads of the substrates include first pads, which are the pads of one of the substrates located in at least one of the corners of the block. The pad surface of each of the first pads includes a first axis extending from the first pad toward the plan view center of the block. The pad surface of each of the first pads has a first length along the corresponding first axis and a second length along a second axis, which is orthogonal to the first axis. The first length is longer than the second length.

Abstract translation: 布线基板包括具有布置在阵列中的基板的块。 该块包括角落和平面图中心。 每个基板包括基板主体。 垫片形成在基板主体上。 每个垫包括垫表面。 衬底的焊盘包括第一焊盘，其是位于块的至少一个角落中的一个衬底的焊盘。 每个第一焊盘的焊盘表面包括从第一焊盘朝向块的平面图中心延伸的第一轴。 每个第一焊盘的焊盘表面具有沿着对应的第一轴线的第一长度和沿着与第一轴线正交的第二轴线的第二长度。 第一长度比第二长度长。

公开(公告)号：US09049787B2

公开(公告)日：2015-06-02

申请号：US13745352

申请日：2013-01-18

Applicant: Molex Incorporated

Inventor： Mark Alan Bugg

IPC: H05K1/09 ,  H05K1/02 ,  H01R9/03 ,  H01R13/6474

CPC classification number: H05K1/0216 ,  H01R9/032 ,  H01R12/57 ,  H01R12/62 ,  H01R12/775 ,  H01R13/6474 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/112 ,  H05K1/117 ,  H05K3/3405 ,  H05K2201/09218 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/09727 ,  H05K2201/10356

Abstract: A paddle card construction disclosed for use in connecting electronic devices together. The paddle card takes the form of a circuit board that has a plurality of conductive contact pads arranged thereon in pairs. The contact pads of each pair are spaced apart from each other to provide a pair of points to which cable wire free ends may be terminated, such as by soldering. The spacing of the pads apart from each other in effect reduces to amount of capacitance in the cable wire termination area on the circuit board, thereby reducing the impedance and insertion loss in that area at high frequencies. The contact pads of each pair may be further interconnected together by a thin, conductive trace that extends lengthwise between the contact pads.

Abstract translation: 公开的用于将电子设备连接在一起的桨卡结构。 桨卡采取电路板的形式，其具有成对地布置在其上的多个导电接触垫。 每对的接触垫彼此间隔开以提供一对点，电缆线自由端可以通过焊接方式终止于该点。 彼此分开的焊盘的间隔实际上减少到电路板上的电缆线端接区域中的电容量，从而降低了在该区域的高频下的阻抗和插入损耗。 每对的接触垫可以通过在接触垫之间纵向延伸的薄导电迹线进一步互连在一起。

公开(公告)号：US20140328523A1

公开(公告)日：2014-11-06

申请号：US14337121

申请日：2014-07-21

Applicant: Xintec Inc.

Inventor： Chao-Yen LIN ,  Yi-Hang LIN

IPC: H01L23/00 ,  G06K9/00 ,  H05K1/18

CPC classification number: H01L24/05 ,  G06K9/0004 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/525 ,  H01L24/08 ,  H01L24/13 ,  H01L24/48 ,  H01L29/06 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/0801 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/3701 ,  H05K1/181 ,  H05K2201/09418 ,  H05K2201/09445 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Abstract translation: 本发明的实施例提供了一种芯片封装，其包括：载体基板; 具有上表面和下表面的半导体衬底，设置在载体衬底上; 位于所述半导体衬底的上表面上的器件区域或感测区域; 导电焊盘，位于所述半导体衬底的上表面上; 导电层，电连接到导电焊盘并从半导体衬底的上表面延伸到半导体衬底的侧壁; 以及位于导电层和半导体衬底之间的绝缘层。

公开(公告)号：US20140202751A1

公开(公告)日：2014-07-24

申请号：US13745352

申请日：2013-01-18

Applicant: Molex Incorporated

Inventor： Mark Alan BUGG

IPC: H01R4/02 ,  H05K1/02

CPC classification number: H05K1/0216 ,  H01R9/032 ,  H01R12/57 ,  H01R12/62 ,  H01R12/775 ,  H01R13/6474 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/112 ,  H05K1/117 ,  H05K3/3405 ,  H05K2201/09218 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/09727 ,  H05K2201/10356

Abstract: A paddle card construction disclosed for use in connecting electronic devices together. The paddle card takes the form of a circuit board that has a plurality of conductive contact pads arranged thereon in pairs. The contact pads of each pair are spaced apart from each other to provide a pair of points to which cable wire free ends may be terminated, such as by soldering. The spacing of the pads apart from each other in effect reduces to amount of capacitance in the cable wire termination area on the circuit board, thereby reducing the impedance and insertion loss in that area at high frequencies. The contact pads of each pair may be further interconnected together by a thin, conductive trace that extends lengthwise between the contact pads.

Abstract translation: 公开的用于将电子设备连接在一起的桨卡结构。 桨卡采取电路板的形式，其具有成对地布置在其上的多个导电接触垫。 每对的接触垫彼此间隔开以提供一对点，电缆线自由端可以通过焊接方式终止于该点。 彼此分开的焊盘的间隔实际上减少到电路板上的电缆线端接区域中的电容量，从而降低了在该区域的高频下的阻抗和插入损耗。 每对的接触垫可以通过在接触垫之间纵向延伸的薄导电迹线进一步互连在一起。

公开(公告)号：US08630098B2

公开(公告)日：2014-01-14

申请号：US12483933

申请日：2009-06-12

Applicant: Lior Handelsman ,  Tzachi Glovinsky ,  Amir Grossberg ,  Sönke Rogalia ,  Heribert Schmidt

Inventor： Lior Handelsman ,  Tzachi Glovinsky ,  Amir Grossberg ,  Sönke Rogalia ,  Heribert Schmidt

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/18 ,  H02M7/003 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0216 ,  H05K1/182 ,  H05K3/0061 ,  H05K2201/09418 ,  H05K2201/10166 ,  H05K2201/10522

Abstract: A circuit board adapted for use in an switching converter for connecting a plurality of switches including a first switch, a second switch, a third switch and a fourth switch. The circuit board has a layout for connecting the switches. The layout is adapted for locating the switches substantially at or symmetrically with respect to the endpoints of a right-angle cross. The right-angle cross is formed from two line segments intersecting with a ninety degree angle. The circuit board may offsets the switches perpendicularly to the line segments at the endpoints of the line segments either in a clockwise or a counterclockwise direction.

Abstract translation: 一种电路板，适用于用于连接包括第一开关，第二开关，第三开关和第四开关的多个开关的开关转换器。 电路板具有用于连接开关的布局。 该布局适于将开关基本上位于或对称地相对于直角十字的端点定位。 直角十字从与九十度角相交的两个线段形成。 电路板可以在线段的端点处以顺时针或逆时针方向垂直于线段偏移开关。

公开(公告)号：US08564966B2

公开(公告)日：2013-10-22

申请号：US12538399

申请日：2009-08-10

Applicant: Wataru Kitagawa ,  Shigeru Yuzawa

Inventor： Wataru Kitagawa ,  Shigeru Yuzawa

IPC: H05K7/00 ,  H01G4/228

CPC classification number: H05K1/0231 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/09418 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611

Abstract: Embodiments of the present invention provide an arrangement structure capable of reducing noise caused by a laminated ceramic capacitor mounted on a printed circuit board. A unit arrangement structure includes ceramic capacitors. Among the laminated ceramic capacitors, capacitors are arranged so that capacitor axes thereof extend along a first axis, while the other ceramic capacitors are arranged so that capacitor axes thereof extend along a second axis crossing the first axis. In accordance with such an arrangement structure, it is possible to effectively suppress noise even in the case of single-side mounting.

Abstract translation: 本发明的实施例提供一种能够降低由安装在印刷电路板上的层叠陶瓷电容器引起的噪声的布置结构。 单元布置结构包括陶瓷电容器。 在层叠陶瓷电容器中，电容器被布置成使得其电容器轴线沿着第一轴线延伸，而其它陶瓷电容器被布置成使得其电容器轴线沿着与第一轴线交叉的第二轴线延伸。 根据这样的结构，即使在单面安装的情况下也能够有效地抑制噪音。

公开(公告)号：US08507321B2

公开(公告)日：2013-08-13

申请号：US13105775

申请日：2011-05-11

Applicant: Chao-Yen Lin ,  Yi-Hang Lin

Inventor： Chao-Yen Lin ,  Yi-Hang Lin

IPC: H01L21/50 ,  H01L23/498

CPC classification number: H01L24/05 ,  G06K9/0004 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/525 ,  H01L24/08 ,  H01L24/13 ,  H01L24/48 ,  H01L29/06 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/0801 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/3701 ,  H05K1/181 ,  H05K2201/09418 ,  H05K2201/09445 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

公开(公告)号：US08427841B2

公开(公告)日：2013-04-23

申请号：US12662218

申请日：2010-04-06

Applicant: Dong-Kil Shin ,  Shle-Ge Lee

Inventor： Dong-Kil Shin ,  Shle-Ge Lee

IPC: H05K7/00

CPC classification number: H05K1/111 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/09427 ,  Y02P70/611 ,  Y02P70/613

Abstract: Provided is an electronic device which may include a first structure having a first surface, a first land region on the first surface, a second structure having a second surface facing the first surface, a second land region on the second surface, and a connection structure between the first and second structures electrically connecting the first land region to the second land region. As provided, the first land region may have a major axis and a minor axis on the first surface and the second land region may have a major axis and a minor axis on the second surface. Furthermore, the major axes of the first and second land regions may have different orientations with respect to one another.

Abstract translation: 提供一种电子设备，其可以包括第一结构，其具有第一表面，第一表面上的第一焊盘区域，具有面向第一表面的第二表面的第二结构，第二表面上的第二焊盘区域，以及连接结构 在第一和第二结构之间，电连接第一焊盘区域和第二焊盘区域。 如上所述，第一焊盘区域可以在第一表面上具有长轴和短轴，并且第二焊盘区域可以在第二表面上具有长轴和短轴。 此外，第一和第二脊区域的长轴可以具有彼此不同的取向。

公开(公告)号：US08110929B2

公开(公告)日：2012-02-07

申请号：US12602462

申请日：2008-05-27

Applicant: Toshikazu Imaoka ,  Tetsuro Sawai ,  Kenichi Kobayashi ,  Atsushi Nakano

Inventor： Toshikazu Imaoka ,  Tetsuro Sawai ,  Kenichi Kobayashi ,  Atsushi Nakano

IPC: H01L23/48

CPC classification number: H05K1/141 ,  H01L24/73 ,  H01L25/0657 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15182 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/181 ,  H05K1/182 ,  H05K3/3436 ,  H05K2201/09136 ,  H05K2201/09418 ,  H05K2201/10545 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor module includes: a substrate having a wiring layer; a first rectangular-shaped semiconductor device mounted on one surface of the substrate; a second rectangular-shaped semiconductor device mounted on the other surface of the substrate. The first semiconductor device is arranged such that each side thereof is not parallel to that of the second semiconductor device, and that the first semiconductor device is superimposed on the second semiconductor device, when seen from the direction perpendicular to the surface of the substrate.

Abstract translation: 半导体模块包括：具有布线层的基板; 安装在所述基板的一个表面上的第一矩形半导体器件; 安装在所述基板的另一表面上的第二矩形半导体器件。 第一半导体器件布置成使得其每侧不与第二半导体器件的平行平行，并且当从垂直于衬底的表面的方向看时，第一半导体器件重叠在第二半导体器件上。

公开(公告)号：US08008786B2

公开(公告)日：2011-08-30

申请号：US12828469

申请日：2010-07-01

Applicant: Tim V. Pham ,  Trent S. Uehling

Inventor： Tim V. Pham ,  Trent S. Uehling

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H05K3/3436 ,  H05K2201/09418 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

Abstract translation: 提供一种半导体器件，其包括具有设置在其上的多个接合焊盘（503）的衬底（501）。 每个接合焊盘在平行于基板的方向上具有长轴和短轴，并且长轴与短轴的比率随着焊盘与基板中心的距离而增加。