公开(公告)号：US20170236810A1

公开(公告)日：2017-08-17

申请号：US15354484

申请日：2016-11-17

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro KURITA ,  Masaya KAWANO ,  Koji SOEJIMA

IPC: H01L25/00 ,  H01L23/00 ,  H01L25/18 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

公开(公告)号：US20170194263A1

公开(公告)日：2017-07-06

申请号：US15464393

申请日：2017-03-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru KATO

IPC: H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/14 ,  H03H7/38

CPC classification number: H01L23/5389 ,  G06K19/077 ,  H01L23/14 ,  H01L23/145 ,  H01L23/29 ,  H01L23/31 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/66 ,  H01L24/17 ,  H01L25/0652 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2924/0002 ,  H01L2924/1421 ,  H01L2924/181 ,  H01L2924/19102 ,  H01L2924/19105 ,  H01Q1/2225 ,  H01Q1/38 ,  H01Q1/405 ,  H01Q7/00 ,  H03H7/38 ,  H04B1/59 ,  H05K1/181 ,  H05K1/185 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/09527 ,  H05K2201/10098 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A composite device includes a substrate and a mounted component mounted on a surface of, or inside, the substrate. The substrate includes a first thermoplastic resin layer. A surface of the mounted component includes a second thermoplastic resin layer that includes a same or a similar material as that of the first thermoplastic resin layer. A bonding layer that bonds the second thermoplastic resin layer and the first thermoplastic resin layer together is provided between the second thermoplastic resin layer and the first thermoplastic resin layer.

公开(公告)号：US09655254B2

公开(公告)日：2017-05-16

申请号：US13551586

申请日：2012-07-17

Applicant: Tzu-Wei Huang

Inventor： Tzu-Wei Huang

IPC: H05K3/46 ,  H05K3/00 ,  B32B37/02 ,  B23K101/42 ,  B32B38/04 ,  H05K3/42

CPC classification number: H05K3/4682 ,  B23K11/11 ,  B23K2101/42 ,  B32B37/0084 ,  B32B37/02 ,  B32B37/04 ,  B32B38/04 ,  B32B38/10 ,  B32B2038/047 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2311/00 ,  B32B2311/12 ,  B32B2457/00 ,  B32B2457/08 ,  H05K1/115 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/02 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/46 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/09918 ,  H05K2203/1536 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.

公开(公告)号：US20170084976A1

公开(公告)日：2017-03-23

申请号：US15364899

申请日：2016-11-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Nobuo IKEMOTO ,  Yuki WAKABAYASHI ,  Shigeru TAGO

IPC: H01P3/08 ,  H05K1/11 ,  H01R12/62 ,  H05K3/46 ,  H01P11/00 ,  H05K1/02 ,  H05K3/36

CPC classification number: H01P3/082 ,  H01P3/08 ,  H01P11/003 ,  H01R12/62 ,  H01R24/50 ,  H01R2103/00 ,  H05K1/0219 ,  H05K1/0225 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0253 ,  H05K1/115 ,  H05K1/118 ,  H05K1/147 ,  H05K3/0052 ,  H05K3/363 ,  H05K3/4623 ,  H05K3/4632 ,  H05K2201/07 ,  H05K2201/09154 ,  H05K2201/0919 ,  H05K2201/09481 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/097 ,  H05K2201/09845 ,  H05K2201/10037 ,  H05K2201/10204 ,  Y10T29/49016

Abstract: In a high frequency signal line, a first signal line extends along a first dielectric element assembly, a first reference ground conductor extends along the first signal line, a second signal line is provided in or on the second dielectric element assembly and extends along the second dielectric element assembly, a second reference ground conductor is provided in or on the second dielectric element assembly and extends along the second signal line. A portion of a bottom surface at an end of the first dielectric element assembly and a portion of the top surface at an end of the second dielectric element assembly are joined together such that a joint portion of the first and second dielectric element assemblies includes a corner. The second signal line and the first signal line are electrically coupled together. The first and second reference ground conductors are electrically coupled together.

公开(公告)号：US09406602B2

公开(公告)日：2016-08-02

申请号：US14606425

申请日：2015-01-27

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/683 ,  H01L23/13 ,  H05K3/00 ,  H05K3/46 ,  H01L23/538 ,  H01L23/498 ,  H01L21/00 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H05K3/28 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

公开(公告)号：US09313904B2

公开(公告)日：2016-04-12

申请号：US14310076

申请日：2014-06-20

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kentaro Kaneko ,  Katsuya Fukase

IPC: H05K1/09 ,  H05K3/46

CPC classification number: H05K3/465 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/4679 ,  H05K2201/09527 ,  H05K2203/025

Abstract: A wiring board includes a first wiring layer including a first conductive layer and a second conductive layer coating a first surface and a side surface of the first conductive layer. A first insulating layer covers a first surface and a side surface of the second conductive layer so as to expose a second surface of the first conductive layer opposite to the first surface of the first conductive layer. A second wiring layer is stacked on a first surface of the first insulating layer and is electrically connected to the first wiring layer. The first surface and the side surface of the first conductive layer are smooth surfaces while the first surface and the side surface of the second conductive layer are roughened-surfaces.

Abstract translation: 布线基板包括第一布线层，第一布线层包括第一导电层和涂覆第一导电层的第一表面和侧表面的第二导电层。 第一绝缘层覆盖第二导电层的第一表面和侧表面，以暴露与第一导电层的第一表面相对的第一导电层的第二表面。 第二布线层堆叠在第一绝缘层的第一表面上并与第一布线层电连接。 第一导电层的第一表面和侧表面是平滑表面，而第二导电层的第一表面和侧表面是粗糙表面。

公开(公告)号：US20150296621A1

公开(公告)日：2015-10-15

申请号：US14748623

申请日：2015-06-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kuniaki YOSUI ,  Masahiro OZAWA

IPC: H05K1/16 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01F17/0006 ,  H01G2/06 ,  H01G4/40 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/19105 ,  H05K1/0313 ,  H05K1/111 ,  H05K1/115 ,  H05K1/165 ,  H05K3/383 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0355 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09672 ,  H05K2201/097 ,  H05K2203/0278 ,  H05K2203/0307

Abstract: Sheets are laminated on each other and pressure bonded with fixtures from upper and lower directions of a lamination direction while being heated to produce a laminated circuit substrate including therein a capacitor and a coil. The capacitor is defined by a first conductor pattern and a second conductor pattern that face each other across thermoplastic resin layers. In the laminated circuit substrate, the first conductor pattern includes a first principal surface, the second conductor pattern includes a second principal surface, the first principal surface faces the second conductor pattern, the second principal surface faces the first conductor pattern, and the first principal surface and the second principal surface are subject to a roughening process.

Abstract translation: 将片材彼此层压并且在层叠方向的上下方向上与固定装置进行加压粘合，同时加热以产生包括电容器和线圈的层叠电路基板。 电容器由通过热塑性树脂层彼此面对的第一导体图案和第二导体图案限定。 在层叠电路衬底中，第一导体图案包括第一主表面，第二导体图案包括第二主表面，第一主表面面向第二导体图案，第二主表面面向第一导体图案，第一主体 表面和第二主表面经受粗糙化处理。

公开(公告)号：US20150294754A1

公开(公告)日：2015-10-15

申请号：US14750365

申请日：2015-06-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroyuki Ohata

IPC: H01B3/30 ,  B32B37/06 ,  B32B37/10 ,  B32B27/08

CPC classification number: H01B3/307 ,  B32B27/08 ,  B32B37/06 ,  B32B37/10 ,  B32B2250/24 ,  B32B2255/10 ,  B32B2305/55 ,  B32B2307/20 ,  B32B2307/206 ,  B32B2457/00 ,  B32B2457/08 ,  C08J3/12 ,  C08J2300/12 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49894 ,  H01L2924/00 ,  H01L2924/0002 ,  H05K1/185 ,  H05K3/4632 ,  H05K2201/0141 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A fibrillated liquid crystal polymer powder containing fibrillated liquid crystal polymer particles. A paste containing a dispersion medium and the fibrillated liquid crystal polymer powder. A method of producing the fibrillated liquid crystal polymer powder. A resin multilayer substrate obtained by laminating a plurality of resin sheets including at least one layer of a liquid crystal polymer sheet. On a surface of at least one layer of the liquid crystal polymer sheet, a thickness adjustment layer made of a fibrillated liquid crystal polymer powder containing fibrillated liquid crystal polymer particles is provided in a region insufficient in thickness when at least the plurality of resin sheets are laminated.

Abstract translation: 含原纤化液晶聚合物颗粒的原纤化液晶聚合物粉末。 含有分散介质和原纤化液晶聚合物粉末的糊状物。 一种生产原纤化液晶聚合物粉末的方法。 通过层压多个包含至少一层液晶聚合物片的树脂片而得到的树脂多层基片。 在液晶聚合物片材的至少一层的表面上，在至少多个树脂片材为厚度的区域中，设置由含有原纤化液晶聚合物粒子的原纤化液晶聚合物粉末制成的厚度调整层 层压。

公开(公告)号：US20150163918A1

公开(公告)日：2015-06-11

申请号：US14627194

申请日：2015-02-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takahiro Baba ,  Yuki Wakabayashi

IPC: H05K1/18 ,  H05K1/03 ,  H05K1/02

CPC classification number: H05K1/183 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1531 ,  H01L2924/19105 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/0326 ,  H05K1/181 ,  H05K1/186 ,  H05K3/4617 ,  H05K2201/0141 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2203/0278 ,  H05K2203/063 ,  H01L2924/00

Abstract: A component-embedded board includes a multilayer board obtained by stacking resin layers and an electronic component in the multilayer board having terminal electrodes on at least one principal face. The resin layers include a first resin layer having a space to accommodate the electronic component and at least one first interlayer connector formed by solidifying a conductive paste outside each of at least three sides of a principal face of the electronic component and a second resin layer having second and third interlayer connectors formed by solidifying a conductive paste. At least one second interlayer connector is positioned outside the three sides of the principal face. The third interlayer connectors are joined to the terminal electrodes. The first resin layer and the second resin layer are adjacent to each other in a stacking direction within the multilayer board. The first interlayer connector and the second interlayer connector are joined.

Abstract translation: 组件嵌入板包括通过在至少一个主面上具有端子电极的多层板中堆叠树脂层和电子部件而获得的多层板。 树脂层包括具有容纳电子部件的空间的第一树脂层和通过使电子部件的主面的至少三面中的每一侧固化导电性糊料而形成的至少一个第一层间连接体，以及具有 通过固化导电膏形成的第二和第三层间连接器。 至少一个第二层间连接器位于主面三面的外侧。 第三层间连接器连接到端子电极。 第一树脂层和第二树脂层在多层基板内沿层叠方向彼此相邻。 第一层间连接器和第二层间连接器接合。

公开(公告)号：US08975750B2

公开(公告)日：2015-03-10

申请号：US14455336

申请日：2014-08-08

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  H01L21/4763

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract translation: 在传统的电子设备及其制造方法中，由于在焊球侧的互连层中使用的树脂受到限制，妨碍了电子设备的成本的降低。 电子设备包括互连层（第一互连层）和互连层（第二互连层）。 第二互连层形成在第一互连层的下表面上。 第二互连层的面积比第一互连层的面积大，并且从第一互连层延伸到外部。