公开(公告)号：US08674376B2

公开(公告)日：2014-03-18

申请号：US13096761

申请日：2011-04-28

Applicant: Chao-Chin Wu ,  Shen-Ta Yang

Inventor： Chao-Chin Wu ,  Shen-Ta Yang

IPC: H01L29/18

CPC classification number: H01L25/0753 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/73265 ,  H05K1/11 ,  H05K2201/0979 ,  H05K2201/10106 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An LED package structure with standby bonding pads for increasing wire-bonding yield includes a substrate unit, a light-emitting unit, a conductive wire unit and a package unit. The substrate unit has a substrate body and a plurality of positive pads and negative pads. The light-emitting unit has a plurality of LED bare chips. The positive electrode of each LED bare chip corresponds to at least two of the positive pads, and the negative electrode of each LED bare chip corresponds to at least two of the negative pads. Each wire is electrically connected between the positive electrode of the LED bare chip and one of the at least two positive pads or between the negative electrode of the LED bare chip and one of the at least two negative pads. The package unit has a light-permitting package resin body on the substrate body to cover the LED bare chips.

Abstract translation: 具有用于提高引线接合成品率的备用接合焊盘的LED封装结构包括基板单元，发光单元，导线单元和封装单元。 基板单元具有基板主体和多个正极焊盘和负极焊盘。 发光单元具有多个LED裸芯片。 每个LED裸芯片的正极对应于至少两个正极焊盘，并且每个LED裸芯片的负电极对应于至少两个负极焊盘。 每条导线电连接在LED裸芯片的正电极和至少两个正极焊盘中的一个之间或LED裸芯片的负电极之间以及至少两个负焊盘中的一个之间。 封装单元在基板主体上具有允许封装的树脂体，以覆盖LED裸芯片。

公开(公告)号：US20140055965A1

公开(公告)日：2014-02-27

申请号：US14069402

申请日：2013-11-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiromichi KITAJIMA

IPC: H05K1/02 ,  H05K7/06 ,  H05K1/18

CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/113 ,  H05K1/181 ,  H05K3/4629 ,  H05K7/06 ,  H05K2201/09381 ,  H05K2201/0979 ,  H05K2201/099 ,  H01L2924/00

Abstract: A via conductor connected to a mounting electrode near a corner portion of a circuit substrate is provided in a position in a corresponding mounting electrode, located closer to the center of the circuit substrate. Thus, concentration of a stress in a portion of the via conductor is effectively reduced, and a break, a chip, or a crack is prevented from occurring to the circuit substrate. Even if the portion located closer to the corner portion of the mounting electrode is peeled from the circuit substrate, the electrical characteristics of the circuit module are secured because disconnection between the corresponding mounting electrode and the via conductor is prevented.

Abstract translation: 连接到电路基板的角部附近的安装电极的通孔导体设置在位于更靠近电路基板的中心的相应的安装电极的位置。 因此，有效地减小了通路导体的一部分中的应力集中，并且防止了对电路基板的破裂，芯片或裂纹的发生。 即使靠近安装电极的角部的部分从电路基板剥离，也可以确保电路模块的电气特性，因为防止了相应的安装电极和通路导体之间的断开。

公开(公告)号：US20140042406A1

公开(公告)日：2014-02-13

申请号：US13932834

申请日：2013-07-01

Applicant: Apple Inc.

Inventor： Brett W. Degner ,  Chieh-Wei Chen ,  Dinesh C. Mathew ,  Paul S. Drzaic ,  Sang Ha Kim ,  Silvio Grespan ,  John Z. Zhong ,  Jean-Pierre Guillou ,  Kuo-Hua Sung ,  Young Bae Park ,  Vasudha Gupta

IPC: H01L27/32

CPC classification number: H01L27/326 ,  G02F1/133305 ,  G02F2001/133388 ,  H01L27/3297 ,  H01L51/0097 ,  H01L2251/5338 ,  H05K1/028 ,  H05K1/189 ,  H05K2201/09036 ,  H05K2201/0979 ,  H05K2201/10128 ,  Y02E10/549

Abstract: An electronic device may be provided with an organic light-emitting diode display with minimized border regions. The border regions may be minimized by providing the display with bent edge portions having neutral plane adjustment features that facilitate bending of the bent edge portions while minimizing damage to the bent edge portions. The neutral plane adjustment features may include a modified backfilm layer of the display in which portions of the backfilm layer are removed in a bend region. A display device may include a substrate, a display panel on the substrate having display pixels, and peripheral circuitry proximate the display panel and configured to drive the display pixels. A portion of the periphery of the substrate may be bent substantially orthogonal to the display panel to reduce an apparent surface area of the display device. The bent portion may include an electrode for communication with the peripheral circuitry.

Abstract translation: 电子设备可以设置有具有最小边界区域的有机发光二极管显示器。 通过为显示器提供具有中立平面调整特征的弯曲边缘部分，可以使边缘区域最小化，这有利于弯曲边缘部分的弯曲同时最小化对弯曲边缘部分的损伤。 中性平面调整特征可以包括显示器的改进的背膜层，其中后膜层的部分在弯曲区域中被去除。 显示装置可以包括衬底，具有显示像素的衬底上的显示面板以及靠近显示面板的外围电路，并被配置为驱动显示像素。 基板的周边的一部分可以基本上垂直于显示面板弯曲，以减少显示装置的表观表面积。 弯曲部分可以包括用于与外围电路通信的电极。

公开(公告)号：US20140034376A1

公开(公告)日：2014-02-06

申请号：US13957017

申请日：2013-08-01

Applicant: Samtec, Inc.

Inventor： Gary Ellsworth BIDDLE

IPC: H05K1/02

CPC classification number: H01P3/081 ,  H01P3/026 ,  H01P5/028 ,  H01P5/08 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/0228 ,  H05K1/0237 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/115 ,  H05K1/118 ,  H05K1/14 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/097 ,  H05K2201/09781 ,  H05K2201/0979

Abstract: A substrate including a first transmission line arranged to transmit electrical signals and including first and second traces and a first dielectric layer. The first and second traces are separated from each other by the first dielectric layer. A printed circuit board includes a first transmission line arranged to transmit electrical signals and including first, second, and third traces; and a first dielectric layer. The first and second traces are separated from the third trace by the first dielectric layer.

Abstract translation: 一种衬底，包括布置成传输电信号并且包括第一和第二迹线的第一传输线和第一介电层。 第一和第二迹线通过第一介电层彼此分离。 印刷电路板包括布置成传输电信号并且包括第一，第二和第三迹线的第一传输线; 和第一电介质层。 第一和第二迹线通过第一介电层与第三迹线分离。

公开(公告)号：US08553426B2

公开(公告)日：2013-10-08

申请号：US13304415

申请日：2011-11-25

Applicant: Tsung-Sheng Huang

Inventor： Tsung-Sheng Huang

IPC: H05K7/00

CPC classification number: H05K1/0265 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/0352 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/09727 ,  H05K2201/0979

Abstract: A circuit board includes a plurality of conductive layers, at least one group of vias, a number of second vias, at least one power supply element, and at least one electronic element. Each conductive layer includes a conductive portion. Both the first vias and the second vias are defined through the conductive layers and electrically connected each conductive layers. The at least one group of first vias surrounds the at least one power supply element. The second vias are arranged along the side of the conductive portion, and positioned between the power supply element and the electronic element. Current from a power supply element flows to the inner conductive layers through the group of surrounding first vias. Current transmission on each conductive layer continuously flows to another conductive layer having a lower resistance through the second vias during transmission.

Abstract translation: 电路板包括多个导电层，至少一组通孔，多个第二通孔，至少一个电源元件和至少一个电子元件。 每个导电层包括导电部分。 第一通孔和第二通孔都通过导电层定义并电连接每个导电层。 所述至少一组第一通孔围绕所述至少一个电源元件。 第二通孔沿着导电部分的侧面布置，并且位于电源元件和电子元件之间。 来自电源元件的电流通过一组周围的第一通孔流到内部导电层。 在传输期间，每个导电层上的电流传输通过第二通孔连续流动到具有较低电阻的另一导电层。

公开(公告)号：US08547677B2

公开(公告)日：2013-10-01

申请号：US13175918

申请日：2011-07-04

Applicant: William M. Anthony ,  David Anthony ,  Anthony Anthony

Inventor： William M. Anthony ,  David Anthony ,  Anthony Anthony

IPC: H02H9/00

CPC classification number: H01G4/35 ,  H01G4/005 ,  H01G4/232 ,  H01G4/30 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/43 ,  Y10T29/49002

Abstract: The application discloses novel internal structures of energy conditioners, assemblies of external structures of energy conditioners and mounting structure, and novel circuits including energy conditioners having A, B, and G master electrodes.

Abstract translation: 该申请公开了能量调节器的新型内部结构，能量调节器的外部结构的组件和安装结构，以及包括具有A，B和G主电极的能量调节器的新颖的电路。

公开(公告)号：US08536462B1

公开(公告)日：2013-09-17

申请号：US12692397

申请日：2010-01-22

Applicant: Robert Francis Darveaux ,  Ludovico E. Bancod ,  Marnie Ann Mattei ,  Timothy Lee Olson

Inventor： Robert Francis Darveaux ,  Ludovico E. Bancod ,  Marnie Ann Mattei ,  Timothy Lee Olson

IPC: H05K1/16 ,  H05K1/00

CPC classification number: H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48265 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/181 ,  H05K3/363 ,  H05K2201/0379 ,  H05K2201/0979 ,  H05K2201/10356 ,  H05K2201/1053 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A flex circuit package includes a package body enclosing an electronic component and a first surface of the substrate. Columns are physically and electrically connected to first traces of the substrate, the columns extending through the package body. A flexible circuit connector has first terminals connected to the columns. The flexible circuit connector further includes second terminals that provide an electrical interconnection structure for electrical connection to a second electronic component structure. By connecting the flexible circuit connector to the columns extending through the package body, special routing of traces of the substrate of the flex circuit package to provide an interface for the flexible circuit connector is avoided.

Abstract translation: 柔性电路封装包括封装电子部件和基板的第一表面的封装体。 柱物理和电连接到衬底的第一迹线，柱延伸穿过封装主体。 柔性电路连接器具有连接到列的第一端子。 柔性电路连接器还包括提供用于与第二电子部件结构电连接的电互连结构的第二端子。 通过将柔性电路连接器连接到延伸穿过封装体的列，避免了柔性电路封装的基板的迹线的特殊布线，以提供用于柔性电路连接器的接口。

公开(公告)号：US20130186960A1

公开(公告)日：2013-07-25

申请号：US13553997

申请日：2012-07-20

Applicant: Hidetoshi SUZUKI ,  Yuichi Hotta ,  Yuji Shimoda ,  Yuuji Ogawa ,  Taku Nishiyama ,  Tadanobu Okubo ,  Junichi Onodera ,  Takeshi Ikuta ,  Naohisa Okumura ,  Katsuyoshi Watanabe ,  Kazuhide Doi

Inventor： Hidetoshi SUZUKI ,  Yuichi Hotta ,  Yuji Shimoda ,  Yuuji Ogawa ,  Taku Nishiyama ,  Tadanobu Okubo ,  Junichi Onodera ,  Takeshi Ikuta ,  Naohisa Okumura ,  Katsuyoshi Watanabe ,  Kazuhide Doi

IPC: G06K19/077

CPC classification number: G06K19/07732 ,  H01L23/3107 ,  H01L23/49838 ,  H01L23/49855 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/165 ,  H01L25/18 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0259 ,  H05K1/0269 ,  H05K1/113 ,  H05K1/117 ,  H05K3/284 ,  H05K3/321 ,  H05K2201/09563 ,  H05K2201/0979 ,  H05K2201/09936 ,  H05K2201/10287 ,  H05K2203/1327 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

Abstract: According to one embodiment, a semiconductor storage device is provided with a memory chip including a storage circuit, a controller chip that controls a memory chip, and a substrate having a first surface and a second surface opposing one another, on the first surface of which the controller chip is mounted. Further, the semiconductor storage device is provided with an external connection terminal formed on the second surface of the substrate, and resin that encapsulates the memory chip, the controller chip, and the substrate, includes a third surface and a fourth surface opposing one another, and has a predetermined mark directly printed only on the fourth surface that is adjacent to the second surface of the substrate.

Abstract translation: 根据一个实施例，半导体存储装置设置有存储芯片，存储芯片包括存储电路，控制存储芯片的控制器芯片和具有第一表面和第二表面的基板，第一表面和第二表面在其第一表面上 安装控制器芯片。 此外，半导体存储装置设置有形成在基板的第二表面上的外部连接端子，并且封装存储芯片，控制器芯片和基板的树脂包括彼此相对的第三表面和第四表面， 并且具有仅在与基板的第二表面相邻的第四表面上直接印刷的预定标记。

公开(公告)号：US08383955B2

公开(公告)日：2013-02-26

申请号：US13097104

申请日：2011-04-29

Applicant: Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho ,  Wei-Chieh Chou

Inventor： Tsung-Sheng Huang ,  Chun-Jen Chen ,  Duen-Yi Ho ,  Wei-Chieh Chou

IPC: H05K1/11

CPC classification number: H05K1/025 ,  H05K1/0265 ,  H05K3/429 ,  H05K2201/0979

Abstract: A printed circuit board (PCB) includes first to fourth layers. A power supply is arranged on the first layer. An electronic component is arranged on the fourth layer. A first via and a second via extend through the PCB and are electrically connected to the electronic component. The PCB further includes third to seventh vias. A length of a transmission path of the current flows from the power supply to electronic component through the third via and the seventh via is almost the same as a length of a transmission path of the current flows from the power supply to the electronic component through the fourth to sixth vias.

Abstract translation: 印刷电路板（PCB）包括第一至第四层。 电源设置在第一层上。 电子部件布置在第四层上。 第一通孔和第二通孔延伸穿过PCB并且电连接到电子部件。 PCB还包括第三至第七个通孔。 通过第三通孔和第七通孔从电源流向电子部件的电流的传输路径的长度与电流从电源流向电子部件的传输路径的长度几乎相同 第四至第六个通道。

公开(公告)号：US20130003333A1

公开(公告)日：2013-01-03

申请号：US13583884

申请日：2011-02-18

Applicant: Hiroshi Toyao ,  Manabu Kusumoto ,  Naoki Kobayashi ,  Noriaki Ando

Inventor： Hiroshi Toyao ,  Manabu Kusumoto ,  Naoki Kobayashi ,  Noriaki Ando

IPC: H05K7/06

CPC classification number: H05K1/0236 ,  H05K1/0218 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09309 ,  H05K2201/09618 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/0979 ,  H05K2201/10371 ,  H05K2201/10674

Abstract: A wiring board includes a metal cap pad that is arranged so as to surround a mounting position of an electronic component and is connected to an end portion of a metal cap, a power source plane that is connected to the electronic component through a connection member and has a gap, a ground plane that is connected to the electronic component through a connection member, and a plurality of conductive body elements that are repeatedly arranged so as to surround the connection members and the gap. The power source plane and the ground plane extend so as to include at least a part of an area that is surrounded by the plurality of conductive body elements and at least a part of an area facing the plurality of conductive body elements.

Abstract translation: 布线基板包括金属盖焊盘，其被设置为围绕电子部件的安装位置并且连接到金属盖的端部，电源平面，其通过连接构件连接到电子部件， 具有间隙，通过连接构件连接到电子部件的接地平面，以及重复地布置成围绕连接构件和间隙的多个导电体元件。 电源平面和接地平面延伸成包括由多个导电体元件围绕的区域的至少一部分和面向多个导电体元件的区域的至少一部分。