公开(公告)号：US20190250502A1

公开(公告)日：2019-08-15

申请号：US16395244

申请日：2019-04-26

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Shih-Lian Cheng ,  Yu-Hua Chen ,  Cheng-Ta Ko ,  Jui-Jung Chien ,  Wei-Tse Ho

IPC: G03F1/50 ,  G03F7/20 ,  H05K3/42 ,  H05K3/18 ,  H05K3/12 ,  H05K3/10 ,  H05K3/00 ,  G01K15/00 ,  G01K7/24 ,  H05K3/24 ,  H05K3/06

CPC classification number: G03F1/50 ,  G01K7/24 ,  G01K15/007 ,  G03F7/2032 ,  G03F7/2047 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/107 ,  H05K3/1275 ,  H05K3/182 ,  H05K3/241 ,  H05K3/422 ,  Y10T29/49124

Abstract: A mask structure and a manufacturing method of the mask structure are provided. The mask structure includes a transparent substrate, a patterned metal layer, and a plurality of microlens structures. The patterned metal layer is disposed on the transparent substrate and exposing a portion of the transparent substrate. The microlens structures are disposed on the transparent substrate exposed by a portion of the patterned metal layer and being in contact with the portion of the patterned metal layer.

公开(公告)号：US20190239362A1

公开(公告)日：2019-08-01

申请号：US16379816

申请日：2019-04-10

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming YANG ,  Chen-Hao LIN ,  Cheng-Ta KO ,  John Hon-Shing LAU ,  Yu-Hua CHEN ,  Tzyy-Jang TSENG

IPC: H05K3/40 ,  H05K1/14 ,  H05K1/11 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H05K1/18

CPC classification number: H05K3/4038 ,  H01L21/4846 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H05K1/11 ,  H05K1/112 ,  H05K1/142 ,  H05K1/183 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49165

Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.

公开(公告)号：US10324370B2

公开(公告)日：2019-06-18

申请号：US15256757

申请日：2016-09-06

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Shih-Lian Cheng ,  Yu-Hua Chen ,  Cheng-Ta Ko ,  Jui-Jung Chien ,  Wei-Tse Ho

IPC: H05K3/00 ,  G03F1/50 ,  H05K3/06 ,  H05K3/24 ,  G01K7/24 ,  G01K15/00 ,  H05K3/10 ,  H05K3/12 ,  H05K3/18 ,  H05K3/42 ,  G03F7/20

Abstract: A manufacturing method of a circuit substrate is provided. A substrate is provided. A positive photoresist layer is coated on the substrate. Once exposure process is performed on the positive photoresist layer disposed on the substrate so as to simultaneously form concaves with at least two different depths.

公开(公告)号：US10271433B2

公开(公告)日：2019-04-23

申请号：US14855404

申请日：2015-09-16

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  Tsung-Yuan Chen ,  Shih-Lian Cheng

IPC: H05K3/30 ,  H05K3/00 ,  H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H05K3/06 ,  H05K3/42 ,  H05K3/46

Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed.

公开(公告)号：US20190109017A1

公开(公告)日：2019-04-11

申请号：US15818777

申请日：2017-11-21

Applicant: Unimicron Technology Corp.

Inventor： Shih-Liang Cheng

IPC: H01L21/48 ,  H05K3/10 ,  H05K3/18

Abstract: A method for manufacturing conductive lines is provided. A first metal layer is formed over a carrier substrate. A second metal layer is formed over the first metal layer. A plurality of first conductive lines is formed on the second metal layer. A protective layer is formed on opposite sidewalls of the first conductive lines. An exposed portion of the second metal layer is removed to expose a portion of the first metal layer. The exposed portion of the first metal layer is removed, and the protective layer is removed.

公开(公告)号：US20190098746A1

公开(公告)日：2019-03-28

申请号：US16203636

申请日：2018-11-29

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min TAIN ,  Kai-Ming YANG ,  Chien-Tsai LI

IPC: H05K1/02 ,  H05K1/11

Abstract: A method for forming a circuit board includes forming a first dielectric layer, a first circuit layer in the first dielectric layer, a second circuit layer on the first dielectric layer, and a plurality of conductive vias in the first dielectric layer and connecting the first circuit layer to the second circuit layer; forming a second dielectric layer on the first dielectric layer and the second circuit layer; forming a plurality of openings in the second dielectric layer to expose a plurality of parts of the second circuit layer; forming a seed layer on the exposed parts of the second circuit layer and sidewalls of the openings; and forming a plurality of bonding layers on the seed layer, wherein the bonding layers and the seed layer are made of copper, and the bonding layers are porous.

公开(公告)号：US20190088401A1

公开(公告)日：2019-03-21

申请号：US15818773

申请日：2017-11-21

Applicant: Unimicron Technology Corp.

Inventor： Chang-Fu Chen ,  Chun-Hao Chen ,  Kuan-Hsi Wu ,  Pi-Te Pan

IPC: H01F27/28 ,  H01F27/24 ,  H05K1/16 ,  H05K1/11

Abstract: A carrier structure includes a substrate, a first patterned circuit layer and at least one magnetic element. The substrate has a first surface and an opening passing through the substrate. The first patterned circuit layer is disposed on the first surface of the substrate and includes an annular circuit for generating an electromagnetic field. The magnetic element is disposed within the opening of the substrate, wherein the magnetic element couples the annular circuit and acts in response to the magnetic force of the electromagnetic field.

公开(公告)号：US10211139B2

公开(公告)日：2019-02-19

申请号：US15287729

申请日：2016-10-06

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Yu-Hua Chen ,  Ra-Min Tain

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/10 ,  H01L21/48 ,  H01L23/367 ,  H01L23/31 ,  C25D5/02 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  H05K1/11 ,  H05K3/46 ,  H01L23/36 ,  H05K3/42

Abstract: A chip package structure including a molding compound, a carrier board, a chip, a plurality of conductive pillars and a circuit board is provided. The carrier board includes a substrate and a redistribution layer. The substrate has a first surface and a second surface. The redistribution layer is disposed on the first surface. The chip and the conductive pillars are disposed on the redistribution layer. The molding compound covers the chip, the conductive pillars, and the redistribution layer. The circuit board is connected with the carrier board, wherein the circuit board is disposed on the molding compound, such that the chip is located between the substrate and the circuit board, and the chip and the redistribution layer are electrically connected with the circuit board through the conductive pillars. Heat generated by the chip is transmitted through the substrate from the first surface to the second surface to dissipate.

公开(公告)号：US10123418B1

公开(公告)日：2018-11-06

申请号：US15903049

申请日：2018-02-23

Applicant: Unimicron Technology Corp.

Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Fu-Yang Chen

IPC: H05K1/16 ,  H05K3/10 ,  H05K1/18 ,  H05K1/02 ,  H01F27/06 ,  H05K1/03 ,  H05K3/00 ,  H01F41/04 ,  H05K1/11

Abstract: A circuit board structure including an insulating layer, first and second dielectric layers, and first and second inductors is provided. The insulating layer includes a first surface, a second surface, and a first conductive through hole. The first dielectric layer is disposed on the first surface. The first inductor is disposed on the first surface and includes a first conductive coil in a solenoid form penetrating the first dielectric layer and a first magnetic flux axis of which the direction is substantially parallel to the first surface. The second dielectric layer is disposed on the second surface. The second inductor is disposed on the second surface and includes a second conductive coil in a solenoid form penetrating the second dielectric layer and a second magnetic flux axis of which the direction is substantially parallel to the second surface. A manufacturing method of a circuit board structure is provided.

公开(公告)号：US10121757B2

公开(公告)日：2018-11-06

申请号：US14953020

申请日：2015-11-27

Applicant: Unimicron Technology Corp.

Inventor： Cheng-Jui Chang

IPC: H01L23/00 ,  H05K1/00

Abstract: A pillar structure is disposed on a substrate. The pillar structure includes a pad, a metal wire bump, a metal wire, and a metal plating layer. The pad is disposed on the substrate. The metal wire bump is disposed on the pad. The metal wire is connected to the metal wire bump. The metal wire extends in a first extension direction, the substrate extends in a second extension direction, and the first extension direction is perpendicular to the second extension direction. The metal plating layer covers the pad and completely encapsulates the metal wire bump and the metal wire.