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公开(公告)号:US10311950B2
公开(公告)日:2019-06-04
申请号:US15706356
申请日:2017-09-15
Applicant: Unity Semiconductor Corporation
Inventor: Lawrence Schloss , Julie Casperson Brewer , Wayne Kinney , Rene Meyer
Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).
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172.
公开(公告)号:US10229739B2
公开(公告)日:2019-03-12
申请号:US15868234
申请日:2018-01-11
Applicant: Unity Semiconductor Corporation
Inventor: Chang Hua Siau , Bruce Lynn Bateman
IPC: G11C11/00 , G11C13/00 , G11C5/06 , G11C5/08 , G11C7/00 , G11C7/18 , G11C7/04 , G11C7/12 , G11C16/24
Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.
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公开(公告)号:US20180364028A1
公开(公告)日:2018-12-20
申请号:US16061268
申请日:2016-12-07
Applicant: UNITY SEMICONDUCTOR
Inventor: Jean-Philippe PIEL , Jeff WuYu SU , Benoît THOUY
Abstract: A device for measuring heights and/or thicknesses on a measurement object, includes (i) a first low-coherence interferometer for combining, in one spectrometer, a reference optical beam and a measurement optical beam originating from reflections of the light on interfaces of the measurement object, to produce a grooved spectrum signal with spectral modulation frequencies, (ii) apparatus for measuring an item of position information representative of the relative optical length, (iii) electronic and calculating apparatus arranged for determining at least one spectral modulation frequency representative of an optical path difference between the measurement optical beam and the reference optical beam, and for determining, by exploiting the item of information and the spectral modulation frequency, at least one height and/or thickness on the measurement object, and (iv) second optical apparatus for measuring distance and/or thickness with a second measurement beam incident on the measurement object on a second face opposite the measurement beam.
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公开(公告)号:US10074420B2
公开(公告)日:2018-09-11
申请号:US15706342
申请日:2017-09-15
Applicant: Unity Semiconductor Corporation
Inventor: Christophe Chevallier , Chang Hua Siau
CPC classification number: G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
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175.
公开(公告)号:US20180231370A1
公开(公告)日:2018-08-16
申请号:US15515407
申请日:2015-09-29
Applicant: UNITY SEMICONDUCTOR
Inventor: Mayeul DURAND DE GEVIGNEY , Philippe GASTALDO
CPC classification number: G01B11/2441 , G01B9/02034 , G01B2210/56 , G01M11/331 , G01N21/8806 , G01N21/9501 , G01N21/9503 , H01L22/12
Abstract: An electronic wafer inspecting method includes: rotating the wavelength transparent wafer, emitting, from a light source coupled with an interferometric device, two light beams, to form, a measurement volume and having a vaiable inter-fringe distance within the volume, a time signature of a defect intersecting the measurement volume depending on an inter-fringe distance where the defect intersects the volume, the device and the wafer arranged so that the measurement volume extends into a wafer region, collecting the light scattered by the wafer region, emitting a signal representing the variation in the intensity of the collected light per time, detecting in the signal, a frequency of the intensity, the frequency being the time of the passge of a defect through the measurement volume, determining, based on the value of the inter-fringe distance at the location where the defect passes, the position of the defect.
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公开(公告)号:US09997241B2
公开(公告)日:2018-06-12
申请号:US15652148
申请日:2017-07-17
Applicant: Unity Semiconductor Corporation
Inventor: Christophe Chevallier , Chang Hua Siau
CPC classification number: G11C13/0023 , G11C8/08 , G11C8/10 , G11C13/0007 , G11C13/0028 , G11C2213/31 , G11C2213/71 , G11C2213/77 , H03K3/356104 , H03K19/018521
Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.
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177.
公开(公告)号:US20170364296A1
公开(公告)日:2017-12-21
申请号:US15631130
申请日:2017-06-23
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor: Chang Hua Siau
IPC: G06F3/06 , G11C5/06 , G11C8/08 , G11C13/00 , G11C11/419
CPC classification number: G06F3/0625 , G06F3/061 , G06F3/0655 , G06F3/0688 , G11C5/06 , G11C8/08 , G11C11/419 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0021 , G11C13/0023 , G11C13/003 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2213/72
Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.
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178.
公开(公告)号:US09830985B2
公开(公告)日:2017-11-28
申请号:US15381566
申请日:2016-12-16
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor: Christophe J. Chevallier , Robert Norman
CPC classification number: G11C13/0035 , G11C5/005 , G11C5/02 , G11C11/16 , G11C13/0002 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/71 , G11C2213/77
Abstract: Methods to maintain values representing data in a memory are disclosed. A method may include identifying a plurality of in-use portions of the memory currently used to store data and recording which in-use portion was a last portion of the memory to be rewritten. Responsive to a trigger signal, data is read from a selected one of the in-use portions of the memory adjacent to the last portion. The method may also include storing the read data into a buffer to form buffered data, and rewriting the buffered data into the memory.
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公开(公告)号:US20170140816A1
公开(公告)日:2017-05-18
申请号:US15366293
申请日:2016-12-01
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor: Christophe J. Chevallier , Chang Hua Siau
IPC: G11C13/00
CPC classification number: G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
Abstract: A memory is described having an array including two-terminal resistive memory elements (MEs) to retain stored data in an absence of electrical power and a disturb isolator circuit operatively coupled to the MEs to compensate for disturbances of a magnitude of a signal associated with a selected two-terminal resistive memory element in the array.
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公开(公告)号:US20160372189A1
公开(公告)日:2016-12-22
申请号:US15181009
申请日:2016-06-13
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor: Bruce Lynn Bateman , Christophe Chevallier , Darrell Rinerson , Chang Hua Siau
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C7/12 , G11C7/22 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/0026 , G11C13/0028 , G11C13/0061 , G11C13/0069 , G11C2013/0045 , G11C2013/0054 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/71 , G11C2213/77
Abstract: A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
Abstract translation: 用于存储器的低读取当前体系结构。 允许交叉点存储器阵列的位线被选择的字线充电,直到确保存储器状态和参考电平之间的最小电压差。
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