公开(公告)号：US09546431B2

公开(公告)日：2017-01-17

申请号：US14185613

申请日：2014-02-20

Applicant: Microfabrica Inc.

Inventor： Adam L. Cohen ,  Michael S. Lockard ,  Kieun Kim ,  Qui T. Le ,  Gang Zhang ,  Uri Frodis ,  Dale S. McPherson ,  Dennis R. Smalley

IPC: C25D5/02 ,  C25D1/00 ,  C23C18/16 ,  B81C1/00

CPC classification number: C25D5/022 ,  B81C1/00126 ,  B81C2201/0109 ,  B81C2201/019 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  Y10T156/11 ,  Y10T156/19

Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations. Other embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer.

Abstract translation: 本发明的一些实施例涉及在电介质或部分电介质基底上建立单层或多层结构的技术。 某些实施方案将种子层材料直接沉积到基底材料上，而其它实施例使用中间粘合层材料。 一些实施例使用不同种子层材料和/或用于牺牲和结构导电建筑材料的粘合层材料。 一些实施例将种子层和/或粘合层材料应用于有选择性的方式，而其它实施例以毯子的方式应用材料。 一些实施例通过平面化操作去除外来沉积物（例如沉积到不想要形成层的一部分的区域），而其他实施例通过蚀刻操作去除外来材料。 其它实施方案涉及使用至少一种导电结构材料，至少一种导电牺牲材料和至少一种电介质材料形成的多层中尺度或微结构结构的电化学制造。 在一些实施方案中，电介质材料是可UV固化的光聚合物。

公开(公告)号：US09493343B2

公开(公告)日：2016-11-15

申请号：US14840453

申请日：2015-08-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Russell T. Herrin ,  Jeffrey C. Maling ,  Anthony K. Stamper

IPC: H05K3/00 ,  B81B3/00 ,  H01L41/113 ,  B81C1/00 ,  H01H57/00 ,  G06F17/50 ,  H01H1/00 ,  H01H59/00

CPC classification number: B81B3/0072 ,  B81B3/0021 ,  B81B2201/01 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00365 ,  B81C1/00476 ,  B81C1/00619 ,  B81C1/00626 ,  B81C1/00666 ,  B81C2201/0109 ,  B81C2201/013 ,  B81C2201/0167 ,  B81C2201/017 ,  B81C2203/0136 ,  B81C2203/0172 ,  G06F17/5068 ,  G06F17/5072 ,  H01H1/0036 ,  H01H57/00 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/1136 ,  H01L2924/0002 ,  Y10S438/937 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/5313 ,  H01L2924/00

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.

Abstract translation: 形成至少一个微电子机械系统（MEMS）的方法包括在远离梁结构的绝缘体层上形成梁结构和电极。 该方法还包括在光束结构上方并且远离电极形成至少一个牺牲层。 该方法还包括在至少一个牺牲层和电极上形成盖结构。 该方法还包括同时提供穿过盖结构的通气孔以暴露牺牲层并在电极上形成部分通孔。 该方法还包括排出牺牲层以形成空腔。 该方法还包括用材料密封通气孔。 该方法还包括通过部分通孔在盖结构中形成最终通孔至电极。

公开(公告)号：US20160228915A1

公开(公告)日：2016-08-11

申请号：US15021962

申请日：2014-09-15

Applicant: KONINKLIJKE PHILPS N.V.

Inventor： PETER DIRKSEN ,  MARCEL MULDER ,  ADRIAAN LEEUWESTEIN

IPC: B06B1/02 ,  B81C1/00 ,  B81B3/00 ,  H02N1/00

CPC classification number: B06B1/0292 ,  B81B3/0021 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00158 ,  B81C2201/0109 ,  B81C2201/013 ,  H02N1/006

Abstract: Disclosed is a method of manufacturing a capacitive micro-machined ultrasonic transducer (CMUT) device comprising a first electrode (112) on a substrate (110) and a second electrode (122) embedded in an electrically insulating membrane, the first electrode and the membrane being separated by a cavity (130) formed by the removal of a sacrificial material (116) in between the first electrode and the membrane, the method comprising forming a membrane portion (22) on the second electrode and a further membrane portion (24) extending from the membrane portion towards the substrate alongside the sacrificial material, wherein the respective thicknesses the membrane portion and the further membrane portion exceed the thickness of the sacrificial material prior to forming said cavity. A CMUT device manufactured in accordance with this method and an apparatus comprising such a CMUT device are also disclosed.

Abstract translation: 公开了一种制造电容微加工超声波换能器（CMUT）装置的方法，该装置包括在基板上的第一电极和埋在电绝缘膜中的第二电极，第一电极和膜 由通过在第一电极和膜之间移除牺牲材料（116）而形成的空腔（130）隔开，所述方法包括在所述第二电极上形成膜部分（22）和另外的膜部分（24） 在牺牲材料旁边从膜部分朝向衬底延伸，其中在形成所述腔体之前，膜部分和另外的膜部分超过牺牲材料的厚度的相应厚度。 还公开了根据该方法制造的CMUT装置和包括这种CMUT装置的装置。

公开(公告)号：US20160078887A1

公开(公告)日：2016-03-17

申请号：US14949638

申请日：2015-11-23

Applicant: Seagate Technology LLC

Inventor： Wei Tian ,  Venkateswara Rao Inturi ,  Dong Lin ,  Huaqing Yin ,  Jiaoming Qiu

IPC: G11B5/31

CPC classification number: G11B5/3176 ,  B81C1/00611 ,  B81C2201/0109 ,  C09K13/00 ,  C23F4/00 ,  G03F7/0041 ,  G11B5/1278 ,  G11B5/187 ,  G11B5/232 ,  G11B5/235 ,  G11B5/3109 ,  G11B5/3116 ,  G11B5/3143 ,  G11B5/3163

Abstract: In accordance with one embodiment, a method may be implemented by depositing a non-magnetic gap layer of material above a main pole layer of magnetic material; depositing a sacrificial layer of material above the non-magnetic gap layer of material; etching a portion of the sacrificial layer of material while not entirely removing the sacrificial layer of material; and depositing additional sacrificial material to the etched sacrificial layer.

Abstract translation: 根据一个实施例，可以通过在磁性材料的主极层之上沉积材料的非磁隙层来实现一种方法; 在材料的非磁隙层之上沉积材料牺牲层; 在不完全去除材料的牺牲层的同时蚀刻材料的牺牲层的一部分; 以及将另外的牺牲材料沉积到蚀刻的牺牲层。

公开(公告)号：US20160055282A1

公开(公告)日：2016-02-25

申请号：US14840422

申请日：2015-08-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Russell T. HERRIN ,  Jeffrey C. MALING ,  Anthony K. STAMPER

IPC: G06F17/50

CPC classification number: B81B3/0072 ,  B81B3/0021 ,  B81B2201/01 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00365 ,  B81C1/00476 ,  B81C1/00619 ,  B81C1/00626 ,  B81C1/00666 ,  B81C2201/0109 ,  B81C2201/013 ,  B81C2201/0167 ,  B81C2201/017 ,  B81C2203/0136 ,  B81C2203/0172 ,  G06F17/5068 ,  G06F17/5072 ,  H01H1/0036 ,  H01H57/00 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/1136 ,  H01L2924/0002 ,  Y10S438/937 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/5313 ,  H01L2924/00

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.

公开(公告)号：US09086431B2

公开(公告)日：2015-07-21

申请号：US13978502

申请日：2012-01-13

Applicant: Edin Sarajlic

Inventor： Edin Sarajlic

IPC: H01R43/00 ,  G01R3/00 ,  B81C1/00 ,  B01L3/00

CPC classification number: G01R3/00 ,  B01L3/502707 ,  B81B2201/057 ,  B81B2203/0118 ,  B81B2203/0338 ,  B81C1/00119 ,  B81C2201/0109 ,  Y10T29/49002

Abstract: The present invention relates to a method of manufacturing a probe comprising a cantilever with a conduit. According to the invention, an etchant window is provided in a layer covering an elongated sacrificial conduit core that is to form the conduit. This allows for an etching process where the elongated sacrificial conduit core is etched away before all material of a substrate is etched away, the remaining material of the substrate material making the probe stronger without being in the way during use of the probe.

Abstract translation: 本发明涉及一种制造探针的方法，该探针包括具有导管的悬臂。 根据本发明，在覆盖要形成导管的细长牺牲导管芯的层中提供蚀刻剂窗口。 这允许蚀刻工艺，其中在衬底的所有材料被蚀刻掉之前，细长的牺牲导管芯被蚀刻掉，使衬底材料的剩余材料在探针的使用期间不会妨碍探针。

公开(公告)号：US08975187B2

公开(公告)日：2015-03-10

申请号：US13925495

申请日：2013-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rueijer Lin ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai

IPC: H01L21/311 ,  B81C1/00 ,  B81B7/00 ,  H01L21/308

CPC classification number: B81C1/00158 ,  B81B7/008 ,  B81B2207/015 ,  B81B2207/096 ,  B81C1/00246 ,  B81C1/00333 ,  B81C1/00539 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2203/0118 ,  B81C2203/0127 ,  B81C2203/0742 ,  B81C2203/0778 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02247 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802

Abstract: Disclosed is a method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.

Abstract translation: 公开了在制造半导体器件期间形成互连的镶嵌工艺中形成氮化钛（TiN）硬掩模的方法，同时控制由TiN硬掩模承载的应力的类型和大小。 TiN硬掩模以多层结构形成，其中通过重复包括TiN和氯PECVD沉积以及N2 / H2等离子体气体处理的工艺循环来连续形成每个子层。 在其形成期间，通过控制TiN子层的数量和等离子体气体处理持续时间来控制由TiN硬掩模承载的应力，使得应力可以平衡在常规制备的TiN硬掩模上预期的预定外部应力 ，这导致沟槽侧壁变形，沟槽开口收缩和间隙填充问题。

公开(公告)号：US20150041932A1

公开(公告)日：2015-02-12

申请号：US14515681

申请日：2014-10-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Russell T. HERRIN ,  Christopher V. JAHNES ,  Anthony K. STAMPER ,  Eric J. WHITE

IPC: B81B3/00

CPC classification number: B81B3/0072 ,  B81B3/0021 ,  B81B2201/01 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00365 ,  B81C1/00476 ,  B81C1/00619 ,  B81C1/00626 ,  B81C1/00666 ,  B81C2201/0109 ,  B81C2201/013 ,  B81C2201/0167 ,  B81C2201/017 ,  B81C2203/0136 ,  B81C2203/0172 ,  G06F17/5068 ,  G06F17/5072 ,  H01H1/0036 ,  H01H57/00 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/1136 ,  H01L2924/0002 ,  Y10S438/937 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49105 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/5313 ,  H01L2924/00

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS.

Abstract translation: 形成至少一个微机电系统（MEMS）空腔的方法包括在布线层和基板上形成第一牺牲腔层。 该方法还包括在第一牺牲腔层上形成绝缘体层。 该方法还包括在绝缘体层上执行反向镶嵌回蚀工艺。 该方法还包括平坦化绝缘体层和第一牺牲腔层。 该方法还包括将第一牺牲腔层排出或剥离到用于MEMS的第一腔的平坦表面。

公开(公告)号：US20140209473A1

公开(公告)日：2014-07-31

申请号：US14185613

申请日：2014-02-20

Applicant: Microfabrica Inc.

Inventor： Adam L. Cohen ,  Michael S. Lockard ,  Kieun Kim ,  Qui T. Le ,  Gang Zhang ,  Uri Frodis ,  Dale S. McPherson ,  Dennis R. Smalley

IPC: C25D5/02

CPC classification number: C25D5/022 ,  B81C1/00126 ,  B81C2201/0109 ,  B81C2201/019 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  Y10T156/11 ,  Y10T156/19

Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations. Other embodiments are directed to the electrochemical fabrication of multilayer mesoscale or microscale structures which are formed using at least one conductive structural material, at least one conductive sacrificial material, and at least one dielectric material. In some embodiments the dielectric material is a UV-curable photopolymer.

Abstract translation: 本发明的一些实施例涉及在电介质或部分电介质基底上建立单层或多层结构的技术。 某些实施方案将种子层材料直接沉积到基底材料上，而其它实施例使用中间粘合层材料。 一些实施例使用不同种子层材料和/或用于牺牲和结构导电建筑材料的粘合层材料。 一些实施例将种子层和/或粘合层材料应用于有选择性的方式，而其它实施例以毯子的方式应用材料。 一些实施例通过平面化操作去除外来沉积物（例如沉积到不想要形成层的一部分的区域），而其他实施例通过蚀刻操作去除外来材料。 其它实施方案涉及使用至少一种导电结构材料，至少一种导电牺牲材料和至少一种电介质材料形成的多层中尺度或微结构结构的电化学制造。 在一些实施方案中，电介质材料是可UV固化的光聚合物。

公开(公告)号：US08722537B2

公开(公告)日：2014-05-13

申请号：US12686878

申请日：2010-01-13

Applicant: Yao-Te Huang ,  Chia-Hua Chu ,  Yu-Nu Hsu ,  Chun-Wen Cheng ,  Li-Chung Peng

Inventor： Yao-Te Huang ,  Chia-Hua Chu ,  Yu-Nu Hsu ,  Chun-Wen Cheng ,  Li-Chung Peng

IPC: H01L21/44

CPC classification number: H01G7/06 ,  B81B2201/0221 ,  B81C1/0015 ,  B81C2201/0109 ,  H01G7/00 ,  H01L28/60

Abstract: MEMS devices and methods for utilizing sacrificial layers are provided. An embodiment comprises forming a first sacrificial layer and a second sacrificial layer over a substrate, wherein the second sacrificial layer acts as an adhesion layer. Once formed, the first sacrificial layer and the second sacrificial layer are patterned such that the second sacrificial layer is undercut to form a step between the first sacrificial layer and the second sacrificial layer. A top capacitor electrode is formed over the second sacrificial layer, and the first sacrificial layer and the second sacrificial layer are removed in order to free the top capacitor electrode.

Abstract translation: 提供了用于利用牺牲层的MEMS器件和方法。 一个实施例包括在衬底上形成第一牺牲层和第二牺牲层，其中第二牺牲层用作粘附层。 一旦形成，第一牺牲层和第二牺牲层被图案化，使得第二牺牲层被底切以在第一牺牲层和第二牺牲层之间形成台阶。 在第二牺牲层上形成顶部电容器电极，并且去除第一牺牲层和第二牺牲层以便释放顶部电容器电极。