公开(公告)号：US09223054B2

公开(公告)日：2015-12-29

申请号：US14371750

申请日：2013-01-11

Applicant: Panasonic Corporation

Inventor： Yosuke Morita

IPC: G01J1/42 ,  G01V8/20 ,  H05K1/02 ,  G01S17/00 ,  G01B11/14 ,  G01S17/02 ,  G01S7/481 ,  G06F3/03 ,  G06F3/0354 ,  H03K17/94 ,  G01J5/08 ,  G01J5/00 ,  H05K3/10 ,  H03K17/945

CPC classification number: G01V8/20 ,  G01B11/14 ,  G01J1/429 ,  G01J5/0025 ,  G01J5/0809 ,  G01J5/0868 ,  G01J5/0896 ,  G01S7/4813 ,  G01S7/4815 ,  G01S17/00 ,  G01S17/026 ,  G06F3/0304 ,  G06F3/03547 ,  H01L2924/15156 ,  H03K17/943 ,  H03K2017/9455 ,  H03K2217/94111 ,  H05K1/0284 ,  H05K3/108 ,  H05K2201/0338 ,  H05K2201/10151 ,  H05K2201/2054

Abstract: A proximity sensor detects an object to be detected. The proximity sensor includes a board; at least three light emitting portions which are mounted on a surface of the board such that not all the light emitting portions is arranged on a straight line, and which emits light; and a light receiving portion which is mounted on the surface of the board so as to have a predetermined positional relationship with the three light emitting portions, and which receives reflected light derived from light emitted from the light emitting portions and reflected by the object to be detected.

Abstract translation: 接近传感器检测要检测的物体。 接近传感器包括板; 至少三个发光部分，其安装在所述板的表面上，使得并非所有的发光部分都布置在直线上，并且发光; 以及光接收部分，其安装在所述板的表面上以与所述三个发光部分具有预定的位置关系，并且其接收从所述发光部分发射并被所述物体反射的光的衍射光的反射光 检测到。

公开(公告)号：US20150319849A1

公开(公告)日：2015-11-05

申请号：US14650416

申请日：2013-12-09

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Yukio SHIMIZU ,  Motoji SHIOTA ,  Hiroki MIYAZAKI ,  Hiroki NAKAHAMA ,  Seiji MURAOKA ,  Takeshi HORIGUCHI

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/32

CPC classification number: H05K1/0274 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/27334 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32227 ,  H01L2224/83851 ,  H01L2224/83874 ,  H01L2924/15788 ,  H01L2924/3511 ,  H05K1/111 ,  H05K3/323 ,  H05K3/4007 ,  H05K2201/0108 ,  H05K2201/0338 ,  H05K2201/10128 ,  Y02P70/611

Abstract: The present invention provides a component securing structure that forms a wiring unit on a TFT glass substrate that is capable of transmitting UV light. A component, such as a driver IC and/or an FPC, is electrically connected to the wiring unit and is secured to the TFT glass substrate by a UV-curable ACF. An opening for transmitting UV light is formed in a light shielding layer of the wiring unit. UV light irradiated from the back side of the TFT glass substrate passes through the opening and directly irradiates the UV-curable ACF.

Abstract translation: 本发明提供一种在能够透射紫外光的TFT玻璃基板上形成布线单元的部件固定结构。 诸如驱动器IC和/或FPC的部件电连接到布线单元并且通过UV可固化ACF固定到TFT玻璃基板。 在布线单元的遮光层中形成用于透射UV光的开口。 从TFT玻璃基板的背面照射的紫外线通过该开口直接照射紫外线固化ACF。

公开(公告)号：US20150216046A1

公开(公告)日：2015-07-30

申请号：US14163389

申请日：2014-01-24

Applicant: Dell Products, LP

Inventor： Stuart Allen Berke ,  Sandor Farkas ,  Bhyrav M. Mutnury

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/18 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K1/0251 ,  H05K1/09 ,  H05K3/429 ,  H05K2201/0338 ,  H05K2201/09509 ,  H05K2201/09536 ,  Y10T29/49004

Abstract: A printed circuit board includes a first trace, a second trace, and a first via. The first trace is in a first conductive layer. The second trace is in a second conductive layer. The first via interconnects the first trace and the second trace, and communicates a first signal from the first trace to the second trace through a third conductive layer. The third conductive layer has a higher impedance than the first conductive layer and the second conductive layer.

Abstract translation: 印刷电路板包括第一迹线，第二迹线和第一通孔。 第一个迹线在第一导电层中。 第二迹线在第二导电层中。 第一通孔互连第一迹线和第二迹线，并且通过第三导电层将来自第一迹线的第一信号传送到第二迹线。 第三导电层的阻抗高于第一导电层和第二导电层。

公开(公告)号：US20150181690A1

公开(公告)日：2015-06-25

申请号：US14516487

申请日：2014-10-16

Applicant: HYUNDAI MOTOR COMPANY ,  KIA MOTORS CORPORATION ,  YURA CORPORATION CO., LTD.

Inventor： Mun Jong KIM ,  Kwan Bum LEE ,  Jin Su YEOM

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/44 ,  H05K3/46 ,  H05K3/00 ,  H05K3/06

CPC classification number: H05K1/0201 ,  H05K1/0206 ,  H05K1/09 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/067 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0338 ,  H05K2201/09045 ,  H05K2203/0278 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T29/49165

Abstract: A heat dissipation printed circuit board includes a metal core, lower and upper insulating layers, first lower and first upper circuit patterns, and second lower and second upper circuit patterns. The lower and upper insulating layers are disposed at a lower side and an upper side of the metal core, respectively. The first lower and first upper circuit patterns are disposed at a lower side of the lower insulating layer and at an upper side of the upper insulating layer, respectively. The second lower and second upper circuit patterns are disposed at a lower side of the first lower circuit pattern and at an upper side of the first upper circuit pattern, respectively. An etching portion in the first lower circuit pattern is filled with the lower insulating layer and an etching portion in the first upper circuit pattern is filled with the upper insulating layer.

Abstract translation: 散热印刷电路板包括金属芯，下绝缘层和上绝缘层，第一下电极图案和第一上电路图案以及第二下电路图案和第二上电路图案。 下绝缘层和上绝缘层分别设置在金属芯的下侧和上侧。 第一下电极和第一上电路图案分别设置在下绝缘层的下侧和上绝缘层的上侧。 第二下电路图案和第二上电路图案分别设置在第一下电路图案的下侧和第一上电路图案的上侧。 第一下部电路图案中的蚀刻部分填充有下部绝缘层，并且第一上部电路图案中的蚀刻部分填充有上部绝缘层。

公开(公告)号：US20150173202A1

公开(公告)日：2015-06-18

申请号：US14403922

申请日：2013-02-14

Applicant: RMT Limited

Inventor： Vasiliy Sergeevich Anosov ,  Vasiliy Vasilevich Volodin ,  Gennadiy Gyusamovich Gromov ,  Elena Vladmirovna Mazikina ,  Aleksandr Aleksandrovich Nazarenko ,  Sergey Sergeevich Ryabov

IPC: H05K3/06 ,  H05K3/24

CPC classification number: H05K3/065 ,  H01L21/4846 ,  H01L23/498 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2203/107 ,  Y10T29/49156 ,  H01L2924/00

Abstract: The invention forms conductive tracks in electronics and microelectronics for the commutation of electronic circuits and semiconductor devices. The method for producing conductive tracks includes applying continuous metallization layers to a non-conductive substrate, forming a metallization pattern, and applying to the formed tracks a protective barrier layer and a layer for soldering and/or welding elements of parts to the conductive tracks. The continuous metallization layers are applied by consecutively applying an adhesive layer, a conductive layer, and a metal layer, acting as a mask, to the non-conductive substrate. To form the metallization pattern, a mask is formed by laser ablation on sections of the metal layer not occupied by conductive tracks, then selective chemical etching removes the conductive layer and adhesive sublayer from the exposed sections, and selective chemical etching removes the mask, after which the protective barrier layer and layer for soldering and/or welding are applied.

Abstract translation: 本发明在用于电子电路和半导体器件的换向的电子和微电子中形成导电轨迹。 用于制造导电迹线的方法包括将连续的金属化层施加到非导电基底上，形成金属化图案，以及向形成的轨道施加保护性阻挡层和用于将元件的元件焊接和/或焊接到导电迹线的层。 连续金属化层通过连续施加作为掩模的粘合剂层，导电层和金属层施加到非导电基材上。 为了形成金属化图案，在未被导电轨迹占据的金属层的部分上通过激光烧蚀形成掩模，然后选择性化学蚀刻从暴露部分去除导电层和粘合剂子层，并且选择性化学蚀刻除去掩模 其中施加用于焊接和/或焊接的保护屏障层和层。

公开(公告)号：US09041166B2

公开(公告)日：2015-05-26

申请号：US14304988

申请日：2014-06-16

Applicant: Subtron Technology Co., Ltd.

Inventor： Ching-Sheng Chen

IPC: H01L21/00 ,  H05K3/28 ,  H05K3/06

CPC classification number: H05K3/28 ,  H05K3/062 ,  H05K2201/0338

Abstract: A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. A covering layer is formed on the surface passivation layer, and the covering layer covers the surface passivation layer.

Abstract translation: 提供一种电路结构的制造方法。 提供具有上表面的金属层。 在金属层上形成表面钝化层。 表面钝化层暴露金属层的上表面的一部分，并且金属层的材料不同于表面钝化层的材料。 在表面钝化层上形成覆盖层，覆盖层覆盖表面钝化层。

公开(公告)号：US09035195B2

公开(公告)日：2015-05-19

申请号：US13674919

申请日：2012-11-12

Applicant: Hsin-Mao Huang ,  Chun-Huang Yu

Inventor： Hsin-Mao Huang ,  Chun-Huang Yu

IPC: H05K1/11 ,  H05K3/24 ,  H05K1/02

CPC classification number: H05K3/242 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/113 ,  H05K1/117 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2203/0228

Abstract: Provided is a circuit board having a tie bar buried therein. The circuit board includes a dielectric stack, at least a first tie bar, at least a first gold finger and at least a first microvia. The dielectric stack includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on the second dielectric layer. The dielectric stack includes a wireline region and a gold finger region. The first tie bar is buried in the gold finger region between the first dielectric layer and the second dielectric layer. The at least a first gold finger is located in the gold finger region on the first dielectric layer. The first microvia is located in the gold finger region in the first dielectric layer, and electrically connects the first gold finger to the first tie bar.

Abstract translation: 提供一种具有埋入其中的连接杆的电路板。 电路板包括电介质叠层，至少第一连接条，至少第一金指和至少第一微孔。 电介质堆叠包括第一电介质层和第二电介质层。 第一电介质层位于第二电介质层上。 电介质堆叠包括有线区域和金指区域。 第一连杆被埋在第一介电层和第二介电层之间的金指区域中。 至少第一金手指位于第一介电层上的金指区域中。 第一微孔位于第一电介质层中的金指区域中，并且将第一金手指电连接到第一连接杆。

公开(公告)号：US20150129288A1

公开(公告)日：2015-05-14

申请号：US14079191

申请日：2013-11-13

Applicant: TAIWAN GREEN POINT ENTERPRISES CO., LTD.

Inventor： Pen-Yi LIAO ,  Tsung-Han WU ,  Fu-Pin TANG ,  Mei-Chun CHEN ,  Yu-Jen CHOU

IPC: H05K1/02 ,  H05K1/03 ,  C25D5/02 ,  H05K1/09 ,  H05K3/46 ,  H05K3/00

CPC classification number: C25D5/02 ,  C23C18/1603 ,  C23C18/1608 ,  C23C18/1653 ,  C25D5/10 ,  H05K3/0026 ,  H05K3/0041 ,  H05K3/108 ,  H05K3/241 ,  H05K2201/0108 ,  H05K2201/0195 ,  H05K2201/0338 ,  H05K2201/09036 ,  H05K2203/054 ,  H05K2203/107

Abstract: A circuit substrate includes: a substrate; an insulating coating layered structure formed on the substrate, having top and bottom surfaces, and formed with a patterned recess that is indented inwardly from the top surface, that is disposed above the bottom surface, and that is defined by a recess-defining wall, the recess-defining wall having a bottom wall portion and a surrounding wall portion that extends upwardly from a periphery of the bottom wall portion; and a patterned metallic layered structure including an electroless plating metal layer formed on the bottom wall portion of the recess-defining wall.

Abstract translation: 电路基板包括：基板; 形成在所述基板上的绝缘涂层分层结构，具有顶表面和底表面，并且形成有从顶表面向内凹入的图案化凹部，其设置在底表面上方，并且由凹陷限定壁限定， 所述凹部限定壁具有从所述底壁部的周边向上延伸的底壁部和周壁部; 以及图案化的金属层状结构，其包括形成在凹陷限定壁的底壁部分上的化学镀金属层。

公开(公告)号：US20150092119A1

公开(公告)日：2015-04-02

申请号：US14040836

申请日：2013-09-30

Applicant: J TOUCH CORPORATION

Inventor： YU-CHOU YEH ,  TSUNG-HER YEH ,  SZU-KAI LIAO ,  CHIU-CHENG TSUI

IPC: H05K1/09 ,  H05K1/03 ,  H05K1/02

CPC classification number: G06F3/041 ,  G06F3/044 ,  G06F2203/04102 ,  G06F2203/04103 ,  H05K1/0274 ,  H05K1/0393 ,  H05K3/386 ,  H05K3/388 ,  H05K2201/0329 ,  H05K2201/0338

Abstract: An electrode structure for a touchscreen is provided. The electrode structure includes a flexible substrate and a plurality of electrode lines, wherein the electrode line includes a first adhesive layer, a second adhesive layer, a conductive layer, a first resist layer and a second resist layer. Through the configuration above, the electrode structure of the present application adheres the flexible substrate strongly by the first adhesive layer, and the second adhesive layer strengthen the adhesion between the first adhesive layer and the conductive layer, so that the conductive layer may be firmly adhered to the flexible substrate, even change the shape of the substrate, the electrode lines are not easy to fall off. The present invention also provides an electrode structure for scattering the reflective metallic luster to make observer imperceptible and reduce the backlight interference.

Abstract translation: 提供了一种用于触摸屏的电极结构。 电极结构包括柔性基板和多条电极线，其中电极线包括第一粘合剂层，第二粘合剂层，导电层，第一抗蚀剂层和第二抗蚀剂层。 通过上述结构，本申请的电极结构通过第一粘合层牢固地粘附柔性基板，并且第二粘合层增强了第一粘合剂层和导电层之间的粘附，使得导电层可以牢固地粘附 对于柔性基板，甚至改变基板的形状，电极线也不容易脱落。 本发明还提供了用于散射反射金属光泽以使观察者不可察觉并减少背光干扰的电极结构。

公开(公告)号：US20150086806A1

公开(公告)日：2015-03-26

申请号：US14556407

申请日：2014-12-01

Applicant: JX Nippon Mining & Metals Corporation

Inventor： Tomota Nagaura ,  Kazuhiko Sakaguchi

IPC: H05K1/09 ,  C25D3/38 ,  C23C18/31 ,  C25D5/14 ,  C25D3/04 ,  C25D3/58 ,  C25D7/06

CPC classification number: H05K1/09 ,  B32B15/01 ,  C23C18/165 ,  C23C18/31 ,  C23C28/023 ,  C25D1/04 ,  C25D3/04 ,  C25D3/12 ,  C25D3/14 ,  C25D3/16 ,  C25D3/38 ,  C25D3/562 ,  C25D3/565 ,  C25D3/58 ,  C25D5/14 ,  C25D7/0614 ,  C25D9/08 ,  C25D11/38 ,  H05K3/025 ,  H05K2201/0317 ,  H05K2201/032 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2203/0307 ,  Y10T428/12438 ,  Y10T428/12493 ,  Y10T428/12514 ,  Y10T428/12611 ,  Y10T428/12667 ,  Y10T428/12861 ,  Y10T428/12882 ,  Y10T428/1291 ,  Y10T428/12931 ,  Y10T428/12944 ,  Y10T428/12958 ,  Y10T428/24917

Abstract: The present invention provides a carrier-attached copper foil, wherein an ultrathin copper foil is not peeled from the carrier prior to the lamination to an insulating substrate, but can be peeled from the carrier after the lamination to the insulating substrate. A carrier-attached copper foil comprising a copper foil carrier, an intermediate layer laminated on the copper foil carrier, and an ultrathin copper layer laminated on the intermediate layer, wherein the intermediate foil is configured with a Ni layer in contact with an interface of the copper foil carrier and a Cr layer in contact with an interface of the ultrathin copper layer, said Ni layer containing 1,000-40,000 μg/dm2 of Ni and said Cr layer containing 10-100 μg/dm2 of Cr is provided.

Abstract translation: 本发明提供一种载体附着铜箔，其中在层压到绝缘基板之前，超薄铜箔不从载体剥离，而是可以在与绝缘基板层合之后从载体上剥离。 一种载体附着铜箔，包括铜箔载体，层压在所述铜箔载体上的中间层和层压在所述中间层上的超薄铜层，其中所述中间箔配置有与所述中间层的界面接触的Ni层 铜箔载体和与超薄铜层的界面接触的Cr层，所述Ni层含有1000-40,000μg/ dm 2的Ni，所述Cr层含有10-100μg/ dm 2的Cr。