公开(公告)号：US07277298B2

公开(公告)日：2007-10-02

申请号：US11237508

申请日：2005-09-27

Applicant: Tohru Ohsaka

Inventor： Tohru Ohsaka

IPC: H05K7/00

CPC classification number: H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/10734 ,  H01L2924/00

Abstract: According to the invention, even when high-speed differential signal pins are arranged on the inner side of a BGA, they can be wired on a printed wiring board at a low cost. In a multi-terminal device (1) having one surface where a large number of connection terminals are arrayed planarly, terminals (3) that need not be electrically connected individually are arranged between differential signal terminals (2) of the multi-terminal device and the periphery of the multi-terminal device.

Abstract translation: 根据本发明，即使高速差分信号引脚布置在BGA的内侧，也可以低成本地布线在印刷电路板上。 在具有平面排列大量连接端子的一个表面的多端子装置（1）中，不需要电连接的端子（3）分别设置在多端子装置的差分信号端子（2）和 多端设备的外围。

公开(公告)号：US07265300B2

公开(公告)日：2007-09-04

申请号：US10800696

申请日：2004-03-16

Applicant: Luc Adriaenssens ,  Amid Hashim ,  Troy Long

Inventor： Luc Adriaenssens ,  Amid Hashim ,  Troy Long

IPC: H05K1/00

CPC classification number: H01R13/6466 ,  H05K1/0228 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K3/4688 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09672 ,  H05K2201/10189

Abstract: A connector is provided for simultaneously improving both the NEXT high frequency performance when low crosstalk plugs are used and the NEXT low frequency performance when high crosstalk plugs are used. The connector includes PCB substrates made of materials having different dielectric frequency characteristics.

Abstract translation: 提供连接器，用于当使用低串扰插头时同时提高NEXT高频性能，并且当使用高串扰插头时NEXT低频性能。 连接器包括由具有不同介电频率特性的材料制成的PCB衬底。

公开(公告)号：US20070194431A1

公开(公告)日：2007-08-23

申请号：US11359863

申请日：2006-02-22

Applicant: David Corisis ,  Lee Kuan ,  Chin Chong

Inventor： David Corisis ,  Lee Kuan ,  Chin Chong

IPC: H01L23/04 ,  H05K1/00

CPC classification number: H05K1/115 ,  G01R31/026 ,  G06F1/16 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0221 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0296 ,  H05K1/18 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/09809 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.

Abstract translation: 电子器件包括具有在衬底中或衬底上延伸的第一和第二对导电迹线的衬底。 第一导电互连构件延伸穿过衬底中的孔并且与第一和第二对中的每一个的第一迹线电连通，而第二导电互连构件延伸穿过孔并与第一导电互连构件中的每一个的第二迹线电连通 和第二对。 第一和第二互连构件彼此间隔开距离，该距离基本上等于分隔每对导电迹线的距离。 电子设备组件包括被配置为通过导电结构将差分信号传输到接收设备的发送设备。 导电结构包括第一和第二对导电迹线，其中第一和第二互连构件之间提供电连通。

公开(公告)号：US20070149057A1

公开(公告)日：2007-06-28

申请号：US11522530

申请日：2006-09-18

Applicant: Thomas Cohen ,  Marc Cartier ,  Mark Gailus

Inventor： Thomas Cohen ,  Marc Cartier ,  Mark Gailus

IPC: H01R13/648

CPC classification number: H05K7/1445 ,  H01R13/514 ,  H01R13/6587 ,  H01R13/6591 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/14 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09718 ,  H05K2201/10189 ,  H05K2203/1572

Abstract: A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line.

Abstract translation: 中平面具有连接第一差分连接器的接触端的第一侧和与第二差分连接器的接触端连接的第一侧相对的第二侧。 中平面包括从第一侧延伸到第二侧的多个通孔，其中通孔在第一侧上提供第一信号发射，而第二信号在第二侧上发射。 第一信号发射被设置成多行，每行具有沿着第一线的第一信号发射，并且第一信号沿着基本上平行于第一线的第二线发射。 第二信号发射被提供在多列中，每列具有沿着第三线的第二信号发射，而第二信号沿着基本上平行于第三线的第四线发射。

公开(公告)号：US07232959B2

公开(公告)日：2007-06-19

申请号：US10957178

申请日：2004-09-30

Applicant: Shou-Kuo Hsu

Inventor： Shou-Kuo Hsu

IPC: H01R12/04

CPC classification number: H05K1/0228 ,  H05K1/0237 ,  H05K2201/09236 ,  H05K2201/09672

Abstract: A printed circuit board and a routing scenario thereof are disclosed. The printed circuit board includes three dielectric layers, two signal layers and several differential pairs. Some differential pairs are disposed in one signal layer, while some differential pairs are interleavingly disposed in the adjacent other signal layer. The differential pairs in one signal layer carries signals that flows to one direction, while the differential pairs in the adjacent signal layer carries signals that flows to an opposite direction. Under such a routing scenario, the crosstalk between differential pairs in adjacent signal layers may be reduced.

Abstract translation: 公开了一种印刷电路板及其路由场景。 印刷电路板包括三个电介质层，两个信号层和几个差分对。 一些差分对设置在一个信号层中，而一些差分对被交织地布置在相邻的其它信号层中。 一个信号层中的差分对携带流向一个方向的信号，而相邻信号层中的差分对携带流向相反方向的信号。 在这种路由情况下，可以减少相邻信号层中的差分对之间的串扰。

公开(公告)号：US20070133182A1

公开(公告)日：2007-06-14

申请号：US11438363

申请日：2006-05-23

Applicant: Chang-Sheng Chen ,  Uei-Ming Jow ,  Ying-Jiunn Lai ,  Chin-Sun Shyu

Inventor： Chang-Sheng Chen ,  Uei-Ming Jow ,  Ying-Jiunn Lai ,  Chin-Sun Shyu

IPC: H05K7/00

CPC classification number: H05K1/162 ,  H03H7/09 ,  H03H7/1775 ,  H03H2001/0085 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/09236 ,  H05K2201/09672

Abstract: A multi-layered printed circuit board embedded with a filter, the multi-layered printed circuit board using a composite multi-layered printed circuit board formed of at least a high dielectric material stacked with at least a low dielectric material. A plurality of serial or parallel capacitors are disposed in the composite multi-layered printed circuit board so as to form a filter. At least one capacitor is an interdigital capacitor disposed on a low dielectric material. Metal electrodes of the interdigital capacitor are located on the same plane such that the area of the metal electrodes or the spacing between the metal electrodes can be adjusted in advance to precisely control the electrical properties such as the center frequency and the transmission loss of the filter. Problems resulting from alignment errors caused in manufacturing the composite multi-layered printed circuit board can also be prevented.

Abstract translation: 嵌入滤光器的多层印刷电路板，使用由至少由至少低介电材料层叠的高介电材料形成的复合多层印刷电路板的多层印刷电路板。 多个串联或并联电容器设置在复合多层印刷电路板中以形成滤波器。 至少一个电容器是设置在低电介质材料上的叉指电容器。 叉指电容器的金属电极位于同一平面上，使得金属电极的面积或金属电极之间的间隔可以预先调整以精确地控制诸如滤波器的中心频率和传输损耗之类的电气特性 。 也可以防止在制造复合多层印刷电路板时引起的对准误差所引起的问题。

公开(公告)号：US07230835B1

公开(公告)日：2007-06-12

申请号：US10623216

申请日：2003-07-18

Applicant: Bilal Ahmad

Inventor： Bilal Ahmad

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/111 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/0268 ,  H05K2201/0792 ,  H05K2201/09236 ,  H05K2201/09281 ,  H05K2201/093 ,  H05K2201/0969 ,  Y02P70/611

Abstract: A circuit board has, in a first signal layer, a signal conductor having a relatively small width and a contact pad having a relatively large width. The relatively large width of the contact pad combined with the relatively narrow signal conductor creates an impedance mismatch between the contact pad and the signal conductor. The circuit board has, in a second signal layer, a ground plane separated from the first signal layer by a nonconductive layer. The circuit board defines an opening in the second signal layer underneath the contact pad. The presence of the ground plane underneath the contact pad typically affects the impedance of the contact pad. The opening in the second signal layer removes a portion the ground plane relative to the contact pad and, therefore, reduces the impedance mismatch between the contact pad and the signal conductor. Such reduction in the mismatch of the impedances between the contact pad and the signal conductor minimizes signal reflection of a signal transmitted through the signal conductor and across the contact pad.

Abstract translation: 电路板在第一信号层中具有相对较小宽度的信号导体和具有相对较大宽度的接触垫。 接触焊盘的相对较大的宽度与较窄的信号导体相结合，在接触焊盘和信号导体之间产生阻抗失配。 电路板在第二信号层中具有通过非导电层与第一信号层分离的接地层。 电路板在接触垫下面的第二信号层中限定开口。 接触焊盘下面的接地层的存在通常会影响接触焊盘的阻抗。 第二信号层中的开口相对于接触焊盘去除接地层的一部分，因此减小了接触焊盘和信号导体之间的阻抗失配。 接触焊盘和信号导体之间的阻抗失配的这种减少使通过信号导体传输的信号和接触焊盘的信号反射最小化。

公开(公告)号：US20070123112A1

公开(公告)日：2007-05-31

申请号：US11670668

申请日：2007-02-02

Applicant: Jack Caveney ,  Scott Lesniak

Inventor： Jack Caveney ,  Scott Lesniak

IPC: H01R24/00

CPC classification number: H01R4/2416 ,  H01R4/2433 ,  H01R13/6466 ,  H01R13/6469 ,  H01R13/665 ,  H01R13/6658 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10S439/942 ,  Y10T29/49201 ,  Y10T29/49202 ,  Y10T29/49204 ,  Y10T29/49208

Abstract: A network cable jack includes a printed circuit board (PCB) for balancing both inductive and capacitive coupling. Using a PCB allows compact trace paths to be formed without significantly increasing manufacturing costs. By including on each trace path two distinct inductance zones separated by a neutral zone, significant gains in degrees of freedom are achieved for designing PCB trace patterns in which a pair of inductive coupling zones jointly offset the inductive coupling caused by a specification plug and the jack contacts, both in magnitude and phase angle. Further, using distinct inductance zones offers more freedom regarding the placement of capacitive plates for use in capacitance balancing as well as the placement of terminals and insulation displacement contacts. Although the magnitude of a capacitive coupling is determined by the length of the capacitor plates parallel to current carrying traces, the approach allows capacitive and inductive coupling to be balanced independently.

Abstract translation: 网络电缆插孔包括用于平衡电感和电容耦合的印刷电路板（PCB）。 使用PCB可以形成紧凑的轨迹路径，而不会显着增加制造成本。 通过在每个迹线路径上包括两个由中性区域分开的不同的电感区域，实现了自由度的显着增益，用于设计PCB迹线图案，其中一对感应耦合区域共同抵消了由规格插头和插孔引起的感性耦合 触点，幅度和相位角。 此外，使用不同的电感区域可以提供更多的自由度，用于电容平板的放置以及端子和绝缘位移触点的放置。 虽然电容耦合的大小由与载流轨迹平行的电容器板的长度确定，但该方法允许电容和电感耦合独立平衡。

公开(公告)号：US20070120192A1

公开(公告)日：2007-05-31

申请号：US11291521

申请日：2005-11-30

Applicant: Jeffrey Dunnihoo ,  Chadwick Marak ,  Michael Evans

Inventor： Jeffrey Dunnihoo ,  Chadwick Marak ,  Michael Evans

IPC: H01L23/62

CPC classification number: H01L23/66 ,  H01L23/49541 ,  H01L23/50 ,  H01L23/60 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/0259 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/10189 ,  H05K2201/10689 ,  H01L2224/45099 ,  H01L2924/00

Abstract: The present invention provides a single ESD device package that can be used to provide ESD protection to multiple high-speed lines, in particular multiple high-speed differential lines. The present invention has various aspects. Minute parasitic matching is achieved within a single package, and TMDS signal discontinuities are reduced by allowing uniform straight through routing. Also, the straight through routing and pin locations are matched to allow those straight routing lines to mate directly to high speed lines. Also, straight ground lines having a single via are associated with the straight through routing lines.

Abstract translation: 本发明提供了可以用于向多条高速线路，特别是多条高速差分线路提供ESD保护的单个ESD器件封装。 本发明具有各个方面。 在单个封装内实现分钟寄生匹配，并通过允许均匀的直通路由降低TMDS信号不连续性。 此外，直通路由和引脚位置匹配，以允许直线路由线直接与高速线路配合。 此外，具有单个通孔的直线接地线与直通路线相关联。

公开(公告)号：US20070097658A1

公开(公告)日：2007-05-03

申请号：US11261014

申请日：2005-10-28

Applicant: Zhiping Yang ,  Vinayagam Arumugham

Inventor： Zhiping Yang ,  Vinayagam Arumugham

IPC: H05K7/06

CPC classification number: H05K1/0245 ,  H01L2223/6638 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/10689

Abstract: A circuit board has a first component interface configured to connect to a first circuit board component, a second component interface configured to connect to a second circuit board component, a differential signal pair electrically connecting the first component interface to the second component interface, and a signal return path configured to operate as a signal return pathway for the differential signal pair. The signal return path includes first conductive material which is in electrical communication with the first component interface, second conductive material which is in electrical communication with the second component interface, and a dielectric which provides direct current separation between the first and second conductive material. Such a circuit board may alleviate the need for DC blocking capacitors along the differential pair, and along other differential pairs when the circuit board has multiple differential pairs connecting the first and second component interfaces.