公开(公告)号：US20110315987A1

公开(公告)日：2011-12-29

申请号：US13225263

申请日：2011-09-02

Applicant: Warren Middlekauff ,  Robert Miller ,  Charlie Centofante

Inventor： Warren Middlekauff ,  Robert Miller ,  Charlie Centofante

IPC: H01L23/495 ,  H01L21/66

CPC classification number: H05K3/28 ,  H01L23/60 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0259 ,  H05K1/0268 ,  H05K1/117 ,  H05K3/284 ,  H05K2201/099 ,  H05K2203/013 ,  H05K2203/161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention concerns covering test contacts (e.g., test pins) provided with the integrated circuit products using printed ink. Once covered with the ink, the test contacts are no longer electrically exposed. Hence, the integrated circuit products are not susceptible to accidental access or electrostatic discharge. Moreover, the integrated circuit products can be efficiently produced in a small form factor without any need for additional packaging or labels to electrically isolate the test contacts.

Abstract translation: 公开了用于生产集成电路产品的改进的技术。 改进的技术允许集成电路产品的生产更小且成本更低。 本发明的一个方面涉及提供使用印刷油墨的集成电路产品的测试接触（例如测试引脚）。 一旦被油墨覆盖，测试触点就不再被电镀。 因此，集成电路产品不易意外进入或静电放电。 此外，集成电路产品可以以小尺寸有效地生产，而不需要额外的封装或标签来电隔离测试触点。

公开(公告)号：US08084869B2

公开(公告)日：2011-12-27

申请号：US12478837

申请日：2009-06-05

Applicant: Takashi Miwa ,  Michiaki Sugiyama ,  Kazumasa Yanagisawa

Inventor： Takashi Miwa ,  Michiaki Sugiyama ,  Kazumasa Yanagisawa

IPC: H01L23/29

CPC classification number: H01L23/49838 ,  H01L21/563 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/4652 ,  H05K2201/09227 ,  H05K2201/099 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A technique permitting the reduction in size of a semiconductor device is provided. In a BGA type semiconductor device with a semiconductor chip flip-chip-bonded onto a wiring substrate, bump electrodes of the semiconductor chip are coupled to lands formed at an upper surface of the wiring substrate. The lands at the upper surface of the wiring substrate are coupled electrically to solder balls formed on a lower surface of the wiring substrate. Therefore, the lands include first type lands with lead-out lines coupled thereto and second type lands with lead-out lines not coupled thereto but with vias formed just thereunder. The lands are arrayed in six or more rows at equal pitches in an advancing direction of the rows. However, a row-to-row pitch is not made an equal pitch. In land rows which are likely to cause a short-circuit, the pitch between adjacent rows is made large, while in land rows which are difficult to cause a short-circuit, the pitch between adjacent rows is made small. By so doing, both prevention of a short-circuit and improvement of the layout density of lands are attained at a time.

Abstract translation: 提供了允许半导体器件的尺寸减小的技术。 在具有倒装芯片接合在布线基板上的半导体芯片的BGA型半导体器件中，半导体芯片的突起电极被耦合到在布线基板的上表面上形成的焊盘。 布线基板的上表面的焊盘电连接到形成在布线基板的下表面上的焊球。 因此，焊盘包括具有与其耦合的引出线的第一类型的焊盘和没有耦合到其上的导出线，但是具有刚好形成的通孔的第二类型的焊盘。 焊盘沿着行的前进方向以等间距排列成六行或更多行。 然而，行到行间距不是相等的音高。 在可能导致短路的陆地列中，相邻行之间的间距变大，而在难以引起短路的陆地行中，相邻行之间的间距变小。 通过这样做，一次可以实现防止短路的改善和布局密度的提高。

公开(公告)号：US08084852B2

公开(公告)日：2011-12-27

申请号：US13020767

申请日：2011-02-03

Applicant: Shinji Moriyama ,  Tomio Yamada

Inventor： Shinji Moriyama ,  Tomio Yamada

IPC: H01L23/52 ,  H01L23/04 ,  H01L23/053 ,  H01L23/12 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/13 ,  H01L23/10 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L24/73 ,  H01L25/165 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H03G3/3042 ,  H05K1/0263 ,  H05K1/141 ,  H05K1/183 ,  H05K3/3405 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/10371 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

公开(公告)号：US08077472B2

公开(公告)日：2011-12-13

申请号：US12211035

申请日：2008-09-15

Applicant: Shu-Tzu Liu

Inventor： Shu-Tzu Liu

IPC: H05K5/00 ,  H05K1/09

CPC classification number: H05K3/0094 ,  H05K1/0215 ,  H05K1/05 ,  H05K1/116 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2201/10409 ,  H05K2203/043

Abstract: A printed circuit board of the present disclosure includes a main body, a tin layer, and a solder mask. The main body defines a through hole configured for being connected to a grounding component. The tin layer is formed on a surface of the main body around the through hole. The tin layer contacts the grounding component. The solder mask is formed between a periphery of the through hole and the tin layer. The solder mask is configured to prevent tin cream of the tin layer from flowing into the through hole.

Abstract translation: 本公开的印刷电路板包括主体，锡层和焊料掩模。 主体限定了连接到接地部件的通孔。 锡层围绕通孔形成在主体的表面上。 锡层接触接地部件。 在通孔的周边和锡层之间形成焊料掩模。 焊锡掩模被配置为防止锡层的锡膏流入通孔。

公开(公告)号：US08039754B2

公开(公告)日：2011-10-18

申请号：US12374123

申请日：2007-05-14

Applicant: Martin Fink ,  Georg Fischer

Inventor： Martin Fink ,  Georg Fischer

IPC: H05K5/03 ,  H05K5/06

CPC classification number: H05K1/118 ,  B60R16/0215 ,  H05K3/365 ,  H05K2201/09363 ,  H05K2201/09381 ,  H05K2201/099 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A conductor carrier includes a base insulating film, a contact insulating film, at least one first printed conductor and one second printed conductor. The contact insulating film includes at least one first recess and one second recess. The printed conductors are embedded between the two insulating films and each forms a first overlapping region with the first or second recess of the contact insulating film. The conductor carrier also includes an insulating region which separates the first printed conductor from the second printed conductor in an insulating manner due to the contact insulating film being less raised than outside the insulating region, and extends between the first and second recesses of the contact insulating film in a meandering manner. A configuration having the conductor carrier is also provided.

Abstract translation: 导体载体包括基底绝缘膜，接触绝缘膜，至少一个第一印刷导体和一个第二印刷导体。 接触绝缘膜包括至少一个第一凹部和一个第二凹部。 印刷的导体嵌入在两个绝缘膜之间，并且每个与接触绝缘膜的第一或第二凹部形成第一重叠区域。 导体载体还包括绝缘区域，其由于接触绝缘膜比绝缘区域外部稍微升高而以绝缘方式将第一印刷导体与第二印刷导体分离，并且在接触绝缘的第一和第二凹部之间延伸 电影以蜿蜒的方式。 还提供了具有导体载体的构造。

公开(公告)号：US20110232951A1

公开(公告)日：2011-09-29

申请号：US13070094

申请日：2011-03-23

Applicant: Shinnosuke MAEDA ,  Tatsuya ITO ,  Satoshi HIRANO

Inventor： Shinnosuke MAEDA ,  Tatsuya ITO ,  Satoshi HIRANO

IPC: H05K1/09

CPC classification number: H05K3/244 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/099 ,  H05K2203/0361 ,  H01L2924/00

Abstract: In a wiring laminate portion of a multilayer wiring substrate, a solder resist layer having a plurality of openings is disposed on a main surface side of the laminate structure, and connection terminals are embedded in an outermost resin insulation layer in contact with the solder resist layer. Each of the connection terminals comprises a copper layer and a metallic layer formed of at least one type of metal other than copper. A main-surface-side circumferential portion of the copper layer is covered by the solder resist layer. At least a portion of the metallic layer is located in a recess in a main-surface-side central portion of the copper layer. At least a portion of the metallic layer is exposed via a corresponding opening.

Abstract translation: 在多层布线基板的布线层叠部分中，具有多个开口的阻焊层设置在层叠结构的主表面侧，并且连接端子嵌入在与阻焊层接触的最外层树脂绝缘层中 。 每个连接端子包括铜层和由铜以外的至少一种类型的金属形成的金属层。 铜层的主表面侧圆周部分被阻焊层覆盖。 金属层的至少一部分位于铜层的主表面侧中央部的凹部中。 金属层的至少一部分经由相应的开口露出。

公开(公告)号：US20110214915A1

公开(公告)日：2011-09-08

申请号：US13109745

申请日：2011-05-17

Applicant: Yoichiro KAWAMURA ,  Shigeki Sawa ,  Katsuhiko Tanno ,  Hironori Tanaka ,  Naoaki Fujii

Inventor： Yoichiro KAWAMURA ,  Shigeki Sawa ,  Katsuhiko Tanno ,  Hironori Tanaka ,  Naoaki Fujii

IPC: H05K1/11

CPC classification number: H05K3/3478 ,  B23K3/0623 ,  B23K2101/42 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/544 ,  H01L24/81 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/3452 ,  H05K2201/0191 ,  H05K2201/099 ,  H05K2203/041 ,  H05K2203/0557 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed wiring board comprises a wiring substrate provided with at least one conductor circuit, a solder resist layer provided on the surface of the wiring substrate, at least one conductor pad formed from a part of the conductor circuit exposed from an opening provided in the solder resist layer, and at least one solder bump for mounting electronic parts on the conductor pad.In the printed wiring board, since the at least one conductor pad is aligned at a pitch of about 200 μm or less, and a ratio (W/D) of a diameter W of the solder bump to an opening diameter D of the opening formed in the solder resist layer is about 1.05 to about 1.7, connection reliability and insulation reliability can be easily improved.

Abstract translation: 一种印刷电路板，包括配置有至少一个导体电路的布线基板，设置在布线基板的表面上的阻焊层，至少一个导体焊盘，由导体电路的一部分露出， 抗蚀剂层和用于将电子部件安装在导体焊盘上的至少一个焊料凸块。 在印刷电路板中，由于至少一个导体焊盘以约200μm以下的间距排列，并且焊料凸块的直径W与形成的开口的开口直径D的比（W / D） 在阻焊层中约1.05〜约1.7，可以容易地提高连接可靠性和绝缘可靠性。

公开(公告)号：US07910838B2

公开(公告)日：2011-03-22

申请号：US12062196

申请日：2008-04-03

Applicant: Glenn Goodman

Inventor： Glenn Goodman

IPC: H05K1/11

CPC classification number: H05K1/141 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/049 ,  H05K2201/0979 ,  H05K2201/099 ,  H05K2201/10689

Abstract: An intercoupling component is provided that electrically connects the device leads of an integrated circuit package to a substrate. The package includes external device leads, each device lead having a downwardly extending section proximate a side of the package body, and the intercoupling component includes an insulating support member. The support member includes a first surface including first electrical attachment sites, each configured for making an electrical connection with a corresponding one of the device leads of the package. The support member also includes an opposite second surface including second electrical attachment sites in electrical contact with the first electrical attachment sites, each of the second electrical attachment sites including a plurality of solder balls associated with each device lead. The plurality of solder balls are used to form an electrical connection between each surface mount pad on the substrate and the corresponding conductive pad of the intercoupling component.

Abstract translation: 提供了将集成电路封装的器件引线电连接到衬底的互耦合部件。 该包装包括外部装置引线，每个装置引线具有靠近封装主体一侧的向下延伸的部分，并且相互联接部件包括绝缘支撑部件。 所述支撑构件包括第一表面，所述第一表面包括第一电连接位置，每个所述第一电连接位置被配置为与所述封装的相应的一个所述器件引线进行电连接。 支撑构件还包括相对的第二表面，其包括与第一电连接位置电接触的第二电附接位置，每个第二电附接位置包括与每个装置引线相关联的多个焊球。 多个焊球用于在基板上的每个表面安装焊盘和相互联结部件的对应导电焊盘之间形成电连接。

公开(公告)号：US20110061232A1

公开(公告)日：2011-03-17

申请号：US12952537

申请日：2010-11-23

Applicant: Yoichiro Kawamura ,  Shigeki Sawa ,  Katsuhiko Tanno ,  Hironori Tanaka ,  Naoaki Fujii

Inventor： Yoichiro Kawamura ,  Shigeki Sawa ,  Katsuhiko Tanno ,  Hironori Tanaka ,  Naoaki Fujii

IPC: H05K3/30

CPC classification number: H05K3/3478 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/3452 ,  H05K2201/0191 ,  H05K2201/099 ,  H05K2203/041 ,  H05K2203/0557 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a printed wiring board including providing a structure having a wiring substrate having a conductor circuit, a build-up multilayer structure formed over the wiring substrate and having an outermost conductor circuit and an outermost insulative resin layer, and a solder resist layer formed over the outermost conductor circuit and outermost insulative resin layer and having openings with an opening diameter D for mounting electronic elements, forming conductor pads with a pitch of about 200 pm or less on the outermost conductor circuit in the openings of the solder resist layer, respectively, and forming solder bumps with a height H from a surface of the solder resist layer on the conductor pads on the conductor pads, respectively, such that a ratio H/D is about 0.55 to about 1.0.

Abstract translation: 一种印刷布线板的制造方法，其特征在于，具备具有布线基板的结构的布线基板，所述布线基板具有导体电路，在所述布线基板上形成的具有最外侧导体电路和最外层绝缘性树脂层的积层叠层结构，以及阻焊层 形成在最外导体电路和最外绝缘树脂层上，具有用于安装电子元件的开口直径D的开口，在阻焊层的开口中的最外导体电路上形成具有约200μm以下间距的导体焊盘， 并且分别在导体焊盘上的导体焊盘上形成具有高度H的阻焊层的焊料凸块，使得H / D的比率为约0.55至约1.0。

公开(公告)号：US20110048782A1

公开(公告)日：2011-03-03

申请号：US12547495

申请日：2009-08-26

Applicant: Jun-Chung Hsu

Inventor： Jun-Chung Hsu

IPC: H05K1/11 ,  B44C1/22

CPC classification number: H05K1/111 ,  H01L2224/05557 ,  H05K3/062 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2203/1184 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49156

Abstract: A solder pad structure with a high bondability to a solder ball is provided. The present invention provides a larger contact area with the solder ball so as to increase the bondability according to the principle that the bondability is positive proportional with the contact area therebetween. The solder pad structure includes a circuit board having a solder pad opening defined by a solder resist layer surrounding a circuit layer. The circuit layer within the solder pad opening is defined as a solder pad. In such a way, after filling the solder ball into the solder pad opening, besides walls of the solder pad opening, there are an extra contact area provided by a geometric shape of the solder pad for further improving the bondability of the solder pad and the solder ball.

Abstract translation: 提供了与焊球具有高粘合性的焊盘结构。 本发明提供了一种与焊球相比较大的接触面积，以便根据粘合性与它们之间的接触面积成正比的原理提高粘接性。 焊盘结构包括具有由围绕电路层的阻焊层限定的焊盘开口的电路板。 焊盘开口内的电路层被定义为焊盘。 以这种方式，在将焊球填充到焊盘开口中之后，除了焊盘开口的壁之外，还存在由焊料焊盘的几何形状提供的额外的接触面积，用于进一步提高焊盘和焊盘的焊接性 焊球