公开(公告)号：US20090201624A1

公开(公告)日：2009-08-13

申请号：US12369759

申请日：2009-02-12

Applicant: Kazuo Hattori ,  Isamu Fujimoto ,  Shinichiro Kuroiwa ,  Satoru Noda

Inventor： Kazuo Hattori ,  Isamu Fujimoto ,  Shinichiro Kuroiwa ,  Satoru Noda

IPC: H01G4/224 ,  H05K1/18

CPC classification number: H05K1/0231 ,  H01G4/224 ,  H01G4/228 ,  H01G4/232 ,  H05K1/185 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A component-embedded substrate includes a chip capacitor. The chip capacitor includes a ceramic laminate body and a plurality of terminal electrodes. The component-embedded substrate has a first principal surface and a second principal surface. At least two of the plurality of terminal electrodes are connected to the first principal surface and define a first terminal electrode group, and at least two of the plurality of terminal electrodes are connected to the second principal surface and define a second terminal electrode group. One terminal electrode in the first terminal electrode group is electrically connected to one terminal electrode in the second terminal electrode group via the internal electrodes, and capacitance is provided by a pair of the terminal electrodes in the first terminal electrode group via the dielectric layer, and capacitance is provided by a pair of the terminal electrodes in the second terminal electrode group via the dielectric layer. A direction in which the internal electrodes are stacked is parallel or substantially parallel to the two principal surfaces.

Abstract translation: 部件嵌入式基板包括片状电容器。 片状电容器包括陶瓷层叠体和多个端子电极。 部件嵌入式基板具有第一主表面和第二主表面。 多个端子电极中的至少两个连接到第一主表面并限定第一端子电极组，并且多个端子电极中的至少两个连接到第二主表面并限定第二端子电极组。 第一端子电极组中的一个端子电极经由内部电极与第二端子组中的一个端子电极电连接，并且电容由第一端子电极组中的一对端子电极经由电介质层提供，以及 电容由第二端子电极组中的一对端子电极经由电介质层提供。 内部电极层叠的方向平行或基本平行于两个主表面。

公开(公告)号：US08878339B2

公开(公告)日：2014-11-04

申请号：US13569454

申请日：2012-08-08

Applicant: Kazuo Hattori ,  Isamu Fujimoto

Inventor： Kazuo Hattori ,  Isamu Fujimoto

IPC: H01L21/02 ,  H01G4/232 ,  H01L49/02 ,  H01G2/06 ,  H05K3/34 ,  H01L23/13 ,  H01L23/498 ,  H01G4/12 ,  H05K1/18

CPC classification number: H01G4/232 ,  H01G2/065 ,  H01G4/12 ,  H01L23/13 ,  H01L23/49805 ,  H01L28/40 ,  H01L2924/0002 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/099 ,  H05K2201/10015 ,  Y02P70/613 ,  H01L2924/00

Abstract: In a chip-component structure, a monolithic ceramic capacitor is a structure including a predetermined number of substantially flat internal electrodes stacked on each other. An interposer includes a substrate larger than the outer shape of the monolithic ceramic capacitor. The substrate includes a first major surface on which first front electrodes for use in mounting the monolithic ceramic capacitor are disposed and a second major surface on which first back electrodes for use in connecting to an external circuit board are disposed. The interposer includes a depression in its side surface. The depression includes a wall surface on which a connection conductor is disposed. The front surface of the substrate is overlaid with resist films extending along its edges.

Abstract translation: 在芯片部件结构中，单片陶瓷电容器是包括彼此堆叠的预定数量的基本平坦的内部电极的结构。 插入器包括比单片陶瓷电容器的外形大的衬底。 基板包括第一主表面，第一主表面设置有用于安装单片陶瓷电容器的第一前电极，并且第二主表面设置有用于连接到外部电路板的第一背电极。 插入件包括其侧表面上的凹陷。 凹陷包括壁表面，连接导体设置在该壁表面上。 衬底的前表面与沿其边缘延伸的抗蚀剂膜重叠。

公开(公告)号：US20130242517A1

公开(公告)日：2013-09-19

申请号：US13616879

申请日：2012-09-14

Applicant: Masanori FUJIDAI ,  Kazuo HATTORI ,  Isamu FUJIMOTO

Inventor： Masanori FUJIDAI ,  Kazuo HATTORI ,  Isamu FUJIMOTO

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0271 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H05K1/182 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611

Abstract: A component assembly that can be easily built in a main substrate with high accuracy is formed such that a glass transition temperature of a built-in-component layer of an assembly substrate in which multiple capacitors are embedded is higher than a glass transition temperature of a built-in-component layer of a built-in-component substrate. Thus, thermal deformation of the component assembly is prevented when the built-in-component substrate in which the component assembly is built is heated during reflow, for example. The component assembly can thus be highly accurately built in the built-in-component substrate. Moreover, when the component assembly in which the multiple capacitors are embedded is built in the built-in-component substrate, electrode pads of the component assembly in which the multiple capacitors are embedded can be electrically connected to wiring layers of the built-in-component substrate by soldering despite the variation in height among the capacitors.

Abstract translation: 可以以高精度容易地构建在主基板中的部件组件被形成为使得嵌入多个电容器的组装基板的内置部件层的玻璃化转变温度高于玻璃化转变温度 内置组件衬底的内置组件层。 因此，例如在回流时，构成部件组件的内置部件基板被加热时，能够防止部件组件的热变形。 因此，组件组件可以高度精确地内置在内置组件衬底中。 此外，在嵌入有多个电容器的部件组装体内置于内置部件基板中时，嵌入多个电容器的部件组装体的电极焊盘能够电连接到内置的多个电容器的配线层， 尽管电容器之间的高度发生变化，仍然通过焊接进行组件衬底。

公开(公告)号：US20130037911A1

公开(公告)日：2013-02-14

申请号：US13569454

申请日：2012-08-08

Applicant: Kazuo HATTORI ,  Isamu FUJIMOTO

Inventor： Kazuo HATTORI ,  Isamu FUJIMOTO

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01G4/232 ,  H01G2/065 ,  H01G4/12 ,  H01L23/13 ,  H01L23/49805 ,  H01L28/40 ,  H01L2924/0002 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/099 ,  H05K2201/10015 ,  Y02P70/613 ,  H01L2924/00

Abstract: In a chip-component structure, a monolithic ceramic capacitor is a structure including a predetermined number of substantially flat internal electrodes stacked on each other. An interposer includes a substrate larger than the outer shape of the monolithic ceramic capacitor. The substrate includes a first major surface on which first front electrodes for use in mounting the monolithic ceramic capacitor are disposed and a second major surface on which first back electrodes for use in connecting to an external circuit board are disposed. The interposer includes a depression in its side surface. The depression includes a wall surface on which a connection conductor is disposed. The front surface of the substrate is overlaid with resist films extending along its edges.

Abstract translation: 在芯片部件结构中，单片陶瓷电容器是包括彼此堆叠的预定数量的基本平坦的内部电极的结构。 插入器包括比单片陶瓷电容器的外形大的衬底。 基板包括第一主表面，第一主表面设置有用于安装单片陶瓷电容器的第一前电极，并且第二主表面设置有用于连接到外部电路板的第一背电极。 插入件包括其侧表面上的凹陷。 凹陷包括壁表面，连接导体设置在该壁表面上。 衬底的前表面与沿其边缘延伸的抗蚀剂膜重叠。

公开(公告)号：US20090166071A1

公开(公告)日：2009-07-02

申请号：US12340965

申请日：2008-12-22

Applicant: Kazuo Hattori ,  Isamu Fujimoto

Inventor： Kazuo Hattori ,  Isamu Fujimoto

IPC: H05K1/18

CPC classification number: H05K1/0231 ,  H01G4/35 ,  H05K1/113 ,  H05K2201/09627

Abstract: An electronic device which includes a feedthrough capacitor mounted on a front surface of a substrate. A feedthrough electrode penetrates a laminate (body of the capacitor). External electrodes are electrically connected to opposite ends of the feedthrough electrode. A capacitor electrode is disposed to form capacity in cooperation with the feedthrough electrode. A wiring conductor is formed on a rear surface of the substrate or inside the substrate, and via-hole conductors are connected to the wiring conductor. The feedthrough electrode and the external electrodes constitute a first current path. The wiring conductor and the via-hole conductors constitute a second current path electrically connected in parallel to the first current path.

Abstract translation: 一种电子装置，其包括安装在基板的前表面上的穿通电容器。 穿通电极穿透层压体（电容器体）。 外部电极电连接到馈通电极的相对端。 配置电容器电极以与馈通电极协作形成容量。 布线导体形成在基板的背面或基板的内部，通孔导体与布线导体连接。 馈通电极和外部电极构成第一电流路径。 布线导体和通孔导体构成与第一电流路并联电连接的第二电流路径。

公开(公告)号：US06243945B1

公开(公告)日：2001-06-12

申请号：US09336531

申请日：1999-06-18

Applicant: Isamu Fujimoto ,  Tohru Yaso ,  Tetsuo Tatsumi

Inventor： Isamu Fujimoto ,  Tohru Yaso ,  Tetsuo Tatsumi

IPC: H05K330

CPC classification number: H01L24/97 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3511 ,  H05K3/0052 ,  H05K3/284 ,  H05K3/403 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49171 ,  Y10T29/49789 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The method of manufacturing electronic parts comprises the steps of: preparing a mother board; mounting element parts on the mother board; providing a thermosetting resin on a surface of the mother board surface on which the element parts are mounted; semi-curing the thermosetting resin so as to be in a range of a stage B condition of the thermosetting resin; splitting the mother board with the thermosetting resin into individual electronic parts each having a divided mother board, at least one element part and the thermosetting resin thereon; and heating the individual electronic parts so that the thermosetting resin in the stage B condition melts first and is then cured permanently.

Abstract translation: 制造电子部件的方法包括以下步骤：准备母板; 在母板上安装元件; 在其上安装有元件部件的母板表面的表面上提供热固性树脂; 将热固性树脂半固化成热固性树脂的B阶段的范围; 将母板与热固性树脂分离成各自具有分开的母板，至少一个元件部分和其上的热固性树脂的电子部件; 并加热各个电子部件，使得阶段B状态下的热固性树脂首先熔化，然后永久固化。

公开(公告)号：US5117100A

公开(公告)日：1992-05-26

申请号：US634566

申请日：1990-12-27

Applicant: Shigeo Yoshida ,  Isamu Fujimoto ,  Hideyuki Suzuki ,  Hiroshi Asano ,  Toru Hosaka ,  Takashi Onioh ,  Kojyu Nagasaki ,  Kenichi Matsuoka ,  Kazufumi Taura

Inventor： Shigeo Yoshida ,  Isamu Fujimoto ,  Hideyuki Suzuki ,  Hiroshi Asano ,  Toru Hosaka ,  Takashi Onioh ,  Kojyu Nagasaki ,  Kenichi Matsuoka ,  Kazufumi Taura

IPC: G01B11/00 ,  G01S5/16 ,  G01S7/48 ,  G01V8/20 ,  G06F3/042

CPC classification number: G01V8/20

Abstract: The present optical position detection method and the apparatus therefor is adapted to compute an arithmetic mean of the adjusted light reception values received by adjacent photodetectors as the virtual light reception value at the virtual position, compare not only the adjusted light reception values of the respective photodetectors but also the virtual light reception values with the reference level and utilize the virtual position also as the light interruption position data when light interruption is determined, thus enhancing the accuracy of detecting the position of an object.

Abstract translation: 本光学位置检测方法及其装置适用于计算由相邻光电检测器接收的调节光接收值的算术平均值作为虚拟位置处的虚拟光接收值，不仅比较各个光电探测器的调节光接收值 而且具有参考电平的虚拟光接收值，并且当确定光中断时也将虚拟位置用作光中断位置数据，从而提高检测对象位置的准确性。