公开(公告)号：US20050188923A1

公开(公告)日：2005-09-01

申请号：US10966245

申请日：2004-10-15

Applicant: Robert Cook ,  Ronald Stevens ,  Peter Schwartz ,  Cesar Tejamo ,  Vebjorn Nilsen ,  Gabriel Ormonde ,  Ajit Paranjpe ,  Somnath Nag ,  Michael Patten

Inventor： Robert Cook ,  Ronald Stevens ,  Peter Schwartz ,  Cesar Tejamo ,  Vebjorn Nilsen ,  Gabriel Ormonde ,  Ajit Paranjpe ,  Somnath Nag ,  Michael Patten

IPC: C23C16/24 ,  C23C16/34 ,  C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C23C16/46 ,  C23C16/48 ,  C23C16/509 ,  C23C16/54 ,  H01J37/32 ,  H01L21/00 ,  H01L21/205 ,  H01L21/318 ,  H01L21/673 ,  H01L21/677 ,  C23C16/00

CPC classification number: H01L21/67303 ,  C23C16/4584 ,  C23C16/54 ,  H01J37/32082 ,  H01J37/32733 ,  H01J2237/2001 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3185 ,  H01L21/67017 ,  H01L21/67069 ,  H01L21/67115 ,  H01L21/67309 ,  H01L21/67346 ,  H01L21/67383

Abstract: A substrate carrier for a parallel wafer processing reactor supports a plurality of substrates. The substrate carrier includes a plurality of susceptors, which may be thermal plates or annular rings that are arranged horizontally in a vertical stack. The substrates are mounted between pairs of susceptors on two or more supports provided around the outer periphery of the susceptors. The number of substrates mounted between each pair of susceptors may the same or different but is two or more between at least one pair of susceptors.

Abstract translation: 用于平行晶片处理反应器的衬底载体支撑多个衬底。 衬底载体包括多个基座，其可以是在垂直堆叠中水平布置的热板或环形环。 衬底被安置在两个或更多个支撑体之间的基座对之间，所述支撑件设置在基座的外周周围。 安装在每对感受体之间的衬底的数量可以相同或不同，但是在至少一对感受器之间是两个或更多个。

公开(公告)号：US08999058B2

公开(公告)日：2015-04-07

申请号：US12774667

申请日：2010-05-05

Applicant: George D. Kamian ,  Somnath Nag ,  Subbu Tamilmani ,  Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  Takao Yonehara

Inventor： George D. Kamian ,  Somnath Nag ,  Subbu Tamilmani ,  Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  Takao Yonehara

IPC: C30B1/10 ,  C25D11/32 ,  H01L31/18 ,  C25D17/00 ,  C25D17/06 ,  C25D11/00

CPC classification number: C25D11/32 ,  C25D11/005 ,  C25D17/001 ,  C25D17/06 ,  C25F3/12 ,  C25F7/00 ,  H01L31/1892 ,  Y02E10/50

Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further the disclosure is applicable to the general fields of Photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

Abstract translation: 本公开使得能够高生产率地制造基于半导体的分离层（由单层或多层多孔半导体（例如多孔硅，包括单孔隙率或多孔度层构成），光反射器（由多层/多孔多孔半导体 孔隙度多孔半导体如多孔硅），用于防反射涂层的多孔半导体（例如多孔硅）的形成，钝化层和多结的多带隙太阳能电池（例如，通过形成可变带隙 晶体硅薄膜或晶圆太阳能电池上的多孔硅发射器）。 其他应用包括制造用于脱模和MEMS器件制造，膜形成和浅沟槽隔离（STI）多孔硅的MEMS分离和牺牲层（使用具有最佳孔隙率并随后氧化的多孔硅形成）。 此外，本公开可应用于光伏，MEMS（包括传感器和致动器）的独立或集成半导体微电子，半导体微电子芯片和光电子学的一般领域。

公开(公告)号：US20080047601A1

公开(公告)日：2008-02-28

申请号：US11841629

申请日：2007-08-20

Applicant: Somnath Nag ,  Mehrdad Moslehi

Inventor： Somnath Nag ,  Mehrdad Moslehi

IPC: H01L31/04 ,  H01L21/00

CPC classification number: H01L31/03529 ,  H01L31/07 ,  Y02E10/50

Abstract: A Schottky contact photovoltaic energy conversion cell. The Schottky contact photovoltaic energy conversion cell comprises a flexible substrate and a first array of a plurality of closely-spaced microscale pillars connected to a first electrical cell contact. The pillars and the contact are formed of (or having a top) layer of a first Schottky metal material with a work function selected for efficiently collecting photogenerated electrons. The Schottky contact photovoltaic energy conversion cell further comprises a second array of a plurality of closely-spaced microscale pillars connected to a second electrical cell contact. The pillars and the contact are formed of (or having a top) layer of a second Schottky metal material with a work function selected for efficiently collecting photogenerated holes. The Schottky contact photovoltaic energy conversion cell further comprises a semiconductor absorber thin-film layer covering the first and second contacts and filling spaces among all the pillars, for creating photogenerated electrons and holes.

Abstract translation: 肖特基接触光伏能量转换电池。 肖特基接触光伏能量转换单元包括柔性基板和连接到第一电单元接触件的多个紧密间隔的微米柱的第一阵列。 柱和接触由具有选择用于有效收集光生电子的功函数的第一肖特基金属材料（或具有顶部）层形成。 肖特基接触光伏能量转换单元还包括连接到第二电池触点的多个紧密间隔的微小柱的第二阵列。 支柱和接触由具有选择用于有效收集光生孔的功函数的（或具有顶部）第二肖特基金属材料层形成。 肖特基接触光伏能量转换单元还包括覆盖所有第一和第二触点和填充空间的半导体吸收体薄膜层，用于产生光生电子和空穴。

公开(公告)号：US20070280526A1

公开(公告)日：2007-12-06

申请号：US11420960

申请日：2006-05-30

Applicant: Irfan Malik ,  Somnath Nag

Inventor： Irfan Malik ,  Somnath Nag

IPC: G06K9/00

CPC classification number: G01N21/9501 ,  G01N21/4738 ,  G06T7/001 ,  G06T2207/30148

Abstract: Various computer-implemented methods are provided. One computer-implemented method for determining information about a defect detected on a wafer after an immersion lithography (IL) process is performed on the wafer includes comparing inspection results for the defect to data in a defect library for different types of IL defects and determining the information about the defect based on results of the comparison. One computer-implemented method for binning defects detected on a wafer after an IL process is performed on the wafer includes comparing one or more characteristics of the defects to one or more characteristics of IL defects and one or more characteristics of non-IL defects. The method also includes binning the defects having one or more characteristics that substantially match the one or more characteristics of the IL defects and the non-IL defects in different groups.

Abstract translation: 提供了各种计算机实现的方法。 在晶片上执行浸没光刻（IL）处理之后，确定关于在晶片上检测到的缺陷的信息的计算机实现方法包括将缺陷的检查结果与不同类型的IL缺陷的缺陷库中的数据进行比较，并且确定 基于比较结果的缺陷信息。 在晶片上执行IL处理之后，在晶片上检测到的缺陷的计算机实现方法包括将缺陷的一个或多个特征与IL缺陷的一个或多个特征以及非IL缺陷的一个或多个特征进行比较。 该方法还包括将具有基本上与不同组中的IL缺陷和非IL缺陷的一个或多个特征基本一致的一个或多个特性的缺陷合并。

公开(公告)号：US20060084283A1

公开(公告)日：2006-04-20

申请号：US10970317

申请日：2004-10-20

Applicant: Ajit Paranjpe ,  Kangzhan Zhang ,  Brendan McDougall ,  Wayne Vereb ,  Michael Patten ,  Alan Goldman ,  Somnath Nag

Inventor： Ajit Paranjpe ,  Kangzhan Zhang ,  Brendan McDougall ,  Wayne Vereb ,  Michael Patten ,  Alan Goldman ,  Somnath Nag

IPC: H01L21/31

CPC classification number: H01L21/0217 ,  C23C16/345 ,  C23C16/4412 ,  C23C16/45525 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/3185

Abstract: A silicon nitride layer is deposited on a substrate within a processing region by introducing a silicon containing precursor into the processing region, exhausting gases in the processing region including the silicon containing precursor while uniformly, gradually reducing a pressure of the processing region, introducing a nitrogen containing precursor into the processing region, and exhausting gases in the processing region including the nitrogen containing precursor while uniformly, gradually reducing a pressure of the processing region. During the steps of exhausting, the slope of the pressure decrease with respect to time is substantially constant.

Abstract translation: 通过将含硅前体引入加工区域，在均匀地引入包含含硅前体的处理区域中的气体中逐渐降低加工区域的压力，引入氮气，在处理区域内的基板上沉积氮化硅层 并且在均匀地排出包含含氮前体的处理区域中的气体，逐渐降低加工区域的压力。 在排气步骤中，压力相对于时间的斜率减小是基本恒定的。

公开(公告)号：US5909628A

公开(公告)日：1999-06-01

申请号：US804484

申请日：1997-02-21

Applicant: Amitava Chatterjee ,  Theodore W. Houston ,  Ih-Chin Chen ,  Agerico L. Esquirel ,  Somnath Nag ,  Iqbal Ali ,  Keith A. Joyner ,  Yin Hu ,  Jeffrey Alan McKee ,  Peter Stewart McAnally

Inventor： Amitava Chatterjee ,  Theodore W. Houston ,  Ih-Chin Chen ,  Agerico L. Esquirel ,  Somnath Nag ,  Iqbal Ali ,  Keith A. Joyner ,  Yin Hu ,  Jeffrey Alan McKee ,  Peter Stewart McAnally

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L21/76229 ,  H01L21/31053 ,  Y10S148/05

Abstract: A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

Abstract translation: 制造半导体器件或集成电路的技术产生平坦化的补充层，其在抛光之后具有比较均匀的厚度，例如通过化学机械抛光（CMP）。 在通常由场氧化物占据的衬底的该部分中的有源区域之间插入虚拟有源区，以便在这些区域中减少在CMP期间发生的“凹陷”。 虚拟有源区域可以采取大块，部分或完全形成的环形结构的形状，或者可以调节其面积密度以匹配衬底的该区域中的有源区的面积密度的多个柱。 支柱的设计规则可以是在多晶硅线或第一级金属化线被放置以避免寄生电容的地方放置柱子。

公开(公告)号：US08926803B2

公开(公告)日：2015-01-06

申请号：US12688495

申请日：2010-01-15

Applicant: Doug Crafts ,  Mehrdad Moslehi ,  Subramanian Tamilmani ,  Joe Kramer ,  George D. Kamian ,  Somnath Nag

Inventor： Doug Crafts ,  Mehrdad Moslehi ,  Subramanian Tamilmani ,  Joe Kramer ,  George D. Kamian ,  Somnath Nag

IPC: C25D17/00 ,  H01L31/18 ,  H01L21/67 ,  H01L21/677

CPC classification number: C25F3/12 ,  C25D11/32 ,  C25F7/00 ,  H01L21/67005 ,  H01L21/67075 ,  H01L21/67086 ,  H01L21/6776 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: It is an object of this disclosure to provide high productivity, low cost-of-ownership manufacturing equipment for the high volume production of photovoltaic (PV) solar cell device architecture. It is a further object of this disclosure to reduce material processing steps and material cost compared to existing technologies by using gas-phase source silicon. The present disclosure teaches the fabrication of a sacrificial substrate base layer that is compatible with a gas-phase substrate growth process. Porous silicon is used as the sacrificial layer in the present disclosure. Further, the present disclosure provides equipment to produce a sacrificial porous silicon PV cell-substrate base layer.

Abstract translation: 本发明的一个目的是提供高生产率，低成本的制造设备用于大量生产光伏（PV）太阳能电池器件结构。 本公开的另一个目的是通过使用气相源硅与现有技术相比减少材料加工步骤和材料成本。 本公开教导了制造与气相衬底生长工艺相容的牺牲衬底基底层。 在本公开中使用多孔硅作为牺牲层。 此外，本公开提供了制造牺牲多孔硅PV电池 - 衬底基底层的设备。

公开(公告)号：US08883552B2

公开(公告)日：2014-11-11

申请号：US13208302

申请日：2011-08-11

Applicant: Ashish Asthana ,  Tirunelveli S. Ravi ,  Kramadhati V. Ravi ,  Somnath Nag

Inventor： Ashish Asthana ,  Tirunelveli S. Ravi ,  Kramadhati V. Ravi ,  Somnath Nag

IPC: H01L21/00 ,  H01L31/18 ,  H01L31/068 ,  H01L31/0224

CPC classification number: H01L31/02245 ,  H01L31/02168 ,  H01L31/03921 ,  H01L31/068 ,  H01L31/1804 ,  H01L31/1892 ,  Y02E10/547 ,  Y02P70/521

Abstract: Methods of fabricating metal wrap through solar cells and modules for thin silicon solar cells, including epitaxial silicon solar cells, are described. These metal wrap through solar cells have a planar back contact geometry for the base and emitter contacts. Fabrication of a metal wrap through solar cell may comprise: providing a photovoltaic device attached at the emitter side of the device to a solar glass by an encapsulant, the device including busbars on the device emitter; forming vias through the device base and emitter, the vias terminating in the busbars; depositing a conformal dielectric film over the surface of the vias and the back surface of the base; removing portions of the conformal dielectric film from the ends of the vias for exposing the busbars and from field areas of the base; and forming separate electrical contacts to the busbars and the field areas on the back surface of the solar cell. The solar cells may comprise epitaxially deposited silicon and may include an epitaxially deposited back surface field.

Abstract translation: 描述了通过太阳能电池制造金属封套的方法和用于薄硅太阳能电池的模块，包括外延硅太阳能电池。 这些金属包裹太阳能电池具有用于基极和发射极触点的平面后接触几何形状。 通过太阳能电池制造金属卷可以包括：通过密封剂将装置的发射极侧附接到太阳能玻璃上的光伏器件，该器件包括器件发射极上的母线; 通过设备基座和发射器形成通孔，终端在母线中的通孔; 在通孔的表面和基底的后表面上沉积保形电介质膜; 从所述通孔的端部去除所述共形绝缘膜的部分，以暴露所述母线和所述基座的场区域; 并且形成与母线和太阳能电池背面上的场区分开的电接触。 太阳能电池可以包括外延沉积的硅并且可以包括外延沉积的背表面场。

公开(公告)号：US08512581B2

公开(公告)日：2013-08-20

申请号：US12193415

申请日：2008-08-18

Applicant: David Xuan-Qi Wang ,  Mehrdad M. Moslehi ,  Somnath Nag

Inventor： David Xuan-Qi Wang ,  Mehrdad M. Moslehi ,  Somnath Nag

IPC: B44C1/22

CPC classification number: B01D1/22 ,  H01L21/02617 ,  H01L21/6715 ,  H01L22/12 ,  H01L31/035281 ,  H01L31/046 ,  H01L31/1872 ,  H01L31/1892 ,  H01L31/202 ,  H05K1/0284 ,  H05K3/046 ,  H05K3/1258 ,  H05K3/207 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2203/0126 ,  H05K2203/0528 ,  H05K2203/308 ,  Y02E10/50 ,  Y02P70/521

Abstract: Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate. Additional features may include filling the micro cavities of the substrate with a filling material, removing the filling material to expose only the substrate surfaces to be coated, coating the substrate with a layer of liquid coating material, and removing said filling material from the micro cavities of the substrate.

Abstract translation: 这里公开的方法提供了选择性地涂覆3-D衬底的顶表面或脊，同时避免液体涂覆材料吸收到3-D衬底上的微腔中。 衬底包括通过在模板上形成牺牲层而形成在三维衬底中的孔。 模板包括具有在柱之间的柱和沟槽的模板衬底。 这些步骤包括随后沉积半导体层并选择性地蚀刻牺牲层。 然后，该步骤包括从模板中释放半导体层并使用用于将液体涂覆材料施加到3-D衬底的表面的液体转移涂覆步骤涂覆3-D衬底。 该方法还可以包括通过选择性地涂覆衬底的顶部脊或表面来涂覆3-D衬底。 附加特征可以包括用填充材料填充衬底的微腔，去除填充材料以仅暴露待涂覆的衬底表面，用一层液体涂覆材料涂覆衬底，以及从微孔中移除所述填充材料 的基底。

公开(公告)号：US20110256654A1

公开(公告)日：2011-10-20

申请号：US13026239

申请日：2011-02-12

Applicant: Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  David Xuan-Qi Wang ,  Pawan Kapur ,  Somnath Nag ,  George D Kamian ,  Jay Ashjaee ,  Takao Yonehara

Inventor： Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  David Xuan-Qi Wang ,  Pawan Kapur ,  Somnath Nag ,  George D Kamian ,  Jay Ashjaee ,  Takao Yonehara

IPC: H01L21/20 ,  C23C16/00 ,  C25D21/12 ,  H01L31/18

CPC classification number: H01L21/20 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.

Abstract translation: 本公开提供了从可再使用的半导体模板的两侧制造TFSS的制造方法和装置设计，从而有效地增加了基板制造的吞吐量并降低了基板的制造成本。 对于给定数量的模板重用周期，这种方法还将每个制造的衬底（TFSS）的平均起始模板成本降低约2倍。