公开(公告)号：US20190219520A1

公开(公告)日：2019-07-18

申请号：US16319455

申请日：2017-06-01

Applicant: UNITY SEMICONDUCTOR

Inventor： Sylvain PETITGRAND

IPC: G01N21/95 ,  G01B11/06 ,  H01L21/673

CPC classification number: G01N21/9501 ,  G01B11/0608 ,  G01R31/2891 ,  H01L21/67346

Abstract: A device for positioning an integrated circuit wafer includes: a base, called upper, and a base, called lower, arranged at a distance from one another in a direction, called vertical, so as to leave a free space between the bases; a support, provided to be mobile between the upper and lower bases, and including a location for receiving the wafer to be inspected; at least one first means apparatus for positioning the support in the vertical direction against, or by cooperation with, the upper base; and at least one second means apparatus for positioning the support in the vertical direction against, or by cooperation with, the lower base. Also provided is an inspection equipment for an integrated circuit wafer implementing such a positioning device.

公开(公告)号：US10260868B2

公开(公告)日：2019-04-16

申请号：US15515407

申请日：2015-09-29

Applicant: UNITY SEMICONDUCTOR

Inventor： Mayeul Durand De Gevigney ,  Philippe Gastaldo

IPC: G01B11/24 ,  G01N21/95 ,  G01N21/88 ,  G01M11/00 ,  G01B9/02 ,  H01L21/66

Abstract: An electronic wafer inspecting method includes: rotating the wavelength transparent wafer, emitting, from a light source coupled with an interferometric device, two light beams, to form, a measurement volume and having a variable inter-fringe distance within the volume, a time signature of a defect intersecting the measurement volume depending on an inter-fringe distance where the defect intersects the volume, the device and the wafer arranged so that the measurement volume extends into a wafer region, collecting the light scattered by the wafer region, emitting a signal representing the variation in the intensity of the collected light per time, detecting in the signal, a frequency of the intensity, the frequency being the time of the passage of a defect through the measurement volume, determining, based on the value of the inter-fringe distance at the location where the defect passes, the position of the defect.

公开(公告)号：US10210917B2

公开(公告)日：2019-02-19

申请号：US15868280

申请日：2018-01-11

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C7/00 ,  G11C7/22 ,  G11C5/02 ,  G11C11/21 ,  G11C13/00 ,  G11C8/10 ,  G11C8/12 ,  B82Y30/00 ,  G11C7/04

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

公开(公告)号：US20190051701A1

公开(公告)日：2019-02-14

申请号：US16042359

申请日：2018-07-23

Applicant: Unity Semiconductor Corporation

Inventor： Lidia Vereen ,  Bruce L. Bateman ,  David A. Eggleston ,  Louis C. Parrillo

IPC: H01L27/24 ,  H01L23/528

CPC classification number: H01L27/249 ,  H01L23/528 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1616

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

公开(公告)号：US20180366194A9

公开(公告)日：2018-12-20

申请号：US15868234

申请日：2018-01-11

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau ,  Bruce Lynn Bateman

IPC: G11C13/00 ,  G11C16/24 ,  G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18

CPC classification number: G11C13/0069 ,  G11C5/06 ,  G11C5/08 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0097 ,  G11C16/24 ,  G11C2213/71

Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.

公开(公告)号：US20180342268A1

公开(公告)日：2018-11-29

申请号：US15984107

申请日：2018-05-18

Applicant: Unity Semiconductor Corporation

Inventor： Chang Hua Siau ,  Christophe Chevallier ,  Darrell Rinerson ,  Seow Fong Lim ,  Sri Rama Namala

IPC: G11C5/02 ,  H01L45/00 ,  G11C13/00 ,  G11C8/00 ,  H01L21/82 ,  G11C11/00 ,  H01L27/24

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

公开(公告)号：US09870809B2

公开(公告)日：2018-01-16

申请号：US15197482

申请日：2016-06-29

Applicant: Unity Semiconductor Corporation

Inventor： Christophe Chevallier ,  Seow Fong Lim ,  Chang Hua Siau

IPC: G11C7/22 ,  G11C5/02 ,  G11C11/21 ,  G11C13/00 ,  G11C8/10 ,  G11C8/12 ,  B82Y30/00 ,  G11C7/04

CPC classification number: G11C7/22 ,  B82Y30/00 ,  G11C5/02 ,  G11C7/04 ,  G11C8/10 ,  G11C8/12 ,  G11C11/21 ,  G11C13/0021

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

公开(公告)号：US09806130B2

公开(公告)日：2017-10-31

申请号：US15393545

申请日：2016-12-29

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Christophe J. Chevallier ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Steven Longcor ,  Darrell Rinerson ,  John Sanchez ,  Philip F. S. Swab ,  Edmond R. Ward

IPC: H01L45/00 ,  G11C11/56 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

公开(公告)号：US20170219496A1

公开(公告)日：2017-08-03

申请号：US15515227

申请日：2015-09-29

Applicant: UNITY SEMICONDUCTOR

Inventor： Mayeul DURAND DE GEVIGNEY ,  Philippe GASTALDO

IPC: G01N21/95 ,  G01N21/88

CPC classification number: G01N21/9505 ,  G01B11/2441 ,  G01M11/331 ,  G01N21/8806 ,  G01N21/8851 ,  G01N21/9501 ,  G01N21/9503 ,  G01N2021/8874

Abstract: A method for inspecting a wafer includes: rotating the wafer about an axis of the wafer, emitting from a light source, two pairs of incident coherent light beams, each pair forming, at the intersection between the two beams, a measurement volume, a portion of the main wafer surface passing through each of the measurement volumes during the rotation, collecting a light beam scattered by the wafer surface, capturing the collected light and emitting an electrical signal representing the variation in the collected light intensity, detecting in the signal, a frequency, being the time signature of a defect through a respective measurement volume, for each detected signature, determining a visibility parameter, on the basis of the visibility determined, obtaining an item of information on the size of the defect, and cross-checking the items of information to determine the size of the defect.

公开(公告)号：US09720611B2

公开(公告)日：2017-08-01

申请号：US15213756

申请日：2016-07-19

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Chang Hua Siau

IPC: G11C11/00 ,  G06F3/06 ,  G11C8/08 ,  G11C11/419 ,  G11C13/00 ,  G11C5/06

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G11C5/06 ,  G11C8/08 ,  G11C11/419 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/72

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.