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    Incremental register retiming of an integrated circuit design
    11.
    发明授权
    Incremental register retiming of an integrated circuit design 有权

    公开(公告)号：US09996652B2

    公开(公告)日：2018-06-12

    申请号：US14846645

    申请日：2015-09-04

    Applicant: Altera Corporation

    Inventor： Nishanth Sinnadurai ,  Gordon Raymond Chiu

    IPC: G06F9/455 ,  G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2217/84

    Abstract: A first circuit design description may have registers and combinational gates. Circuit design computing equipment may perform register retiming on the first circuit design description, whereby registers are moved across combinational gates during a first circuit design implementation. An engineering-change-order (ECO) of the first circuit design may result in a second circuit design. The differences between the first and second circuit designs may be confined to a region-of-change. The circuit design computing equipment may preserve the results from the first circuit design implementation and re-use portions of these results during the implementation of the second circuit design. For example, the circuit design computing equipment may preserve the register retiming solution from the first circuit design implementation for portions of the second circuit design that are outside the region-of-change and incrementally create graphs that allow to incrementally solve the register retiming problem during the second circuit design implementation.

    FAST FILTERING
    12.
    发明申请
    FAST FILTERING 审中-公开

    公开(公告)号：US20180074787A1

    公开(公告)日：2018-03-15

    申请号：US15266179

    申请日：2016-09-15

    Applicant: Altera Corporation

    Inventor： Utku Aydonat ,  Andrew Chaang Ling ,  Gordon Raymond Chiu ,  Shane O'Connell

    IPC: G06F7/44 ,  G06F17/50 ,  G06F17/30

    CPC classification number: G06F7/44 ,  G06F17/5054

    Abstract: Devices and methods for filtering data include calculating intermediate input values from input elements using a transformation function. The transformation function is based at least in part on a size of the filter and a number of filter outputs. Intermediate filter values are calculated from filter elements of the filter using the transformation function. Each intermediate input value is multiplied with a respective intermediate filter value to form intermediate values. These intermediate values are combined with each other using the transformation function to determine one or more output values.

    Speculative circuit design component graphical user interface
    15.
    发明授权
    Speculative circuit design component graphical user interface 有权
    投机电路设计组件图形用户界面

    公开(公告)号：US09529952B1

    公开(公告)日：2016-12-27

    申请号：US14704721

    申请日：2015-05-05

    Applicant: ALTERA CORPORATION

    Inventor： Benjamin Michael Joshua Gamsa ,  Gordon Raymond Chiu

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F17/5054 ,  G06F2217/84

    Abstract: In one embodiment, a tangible, non-transitory, computer-readable medium, includes instructions to receive a first circuit design, determine one or more variations of the first circuit design using register retiming with speculative circuit design changes, determine one or more performance improvements of the variations when fed clock signals over the first circuit design, determine one or more tradeoffs of the one or more variations of the first circuit design in comparison to the first circuit design, display a summary of the one or more variations of the first circuit design, the one or more performance improvements, and the one or more tradeoffs, and provide a user-selectable user interface element to enable selection of the first circuit design, at least one of the one or more variations of the first circuit design, or a combination thereof.

    Abstract translation: 在一个实施例中，有形的，非暂时的计算机可读介质包括接收第一电路设计的指令，使用具有推测电路设计变化的寄存器重新定时确定第一电路设计的一个或多个变型，确定一个或多个性能改进 当通过第一电路设计馈送时钟信号时的变化确定与第一电路设计相比第一电路设计的一个或多个变化的一个或多个权衡，显示第一电路的一个或多个变型的概述 设计，一个或多个性能改进以及一个或多个权衡，并且提供用户可选择的用户界面元件以使得能够选择第一电路设计，第一电路设计的一个或多个变型中的至少一个，或 其组合。

    Techniques for compiling and generating a performance analysis for an integrated circuit design
    16.
    发明授权
    Techniques for compiling and generating a performance analysis for an integrated circuit design 有权
    用于编译和生成集成电路设计性能分析的技术

    公开(公告)号：US09489480B1

    公开(公告)日：2016-11-08

    申请号：US14295752

    申请日：2014-06-04

    Applicant: Altera Corporation

    Inventor： Gordon Raymond Chiu ,  Benjamin Gamsa ,  Paul Mark Leventis

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5022 ,  G06F17/505

    Abstract: Techniques for compiling an integrated circuit (IC) design with an electronic design automation (EDA) tool are provided. The IC design may be compiled for different IC devices. When the IC design is compiled for a selected integrated circuit device, the EDA tool may analyze the IC design to determine whether the design is compatible with the selected IC device. If the IC design contains elements that are incompatible with the selected IC device, the EDA tool may compile the design based on a simulated removal of the incompatible elements. In some instances, the EDA tool may identify optimization opportunities in the IC design and may compile the design based on an optimized version of the IC design. The EDA tool may generate a compilation output (e.g., a performance analysis report) based on the simulated removal of the incompatible elements (or the optimized version of the IC design.

    Abstract translation: 提供了使用电子设计自动化（EDA）工具编译集成电路（IC）设计的技术。 IC设计可以针对不同的IC器件进行编译。 当为所选择的集成电路器件编译IC设计时，EDA工具可以分析IC设计，以确定设计是否与选定的IC器件兼容。 如果IC设计包含与所选IC器​​件不兼容的元件，则EDA工具可以基于模拟删除不兼容元素来编译设计。 在某些情况下，EDA工具可以识别IC设计中的优化机会，并且可以基于IC设计的优化版本来编译设计。 EDA工具可以基于不兼容元件（或IC设计的优化版本）的模拟移除来生成编译输出（例如，性能分析报告）。

    Timing analysis with end-of-life pessimism removal
    18.
    发明授权
    Timing analysis with end-of-life pessimism removal 有权
    消除死亡悲观情绪的时机分析

    公开(公告)号：US08977998B1

    公开(公告)日：2015-03-10

    申请号：US13773468

    申请日：2013-02-21

    Applicant: Altera Corporation

    Inventor： Navid Azizi ,  Gordon Raymond Chiu ,  Ian Carlos Kuon ,  John Curtis Van Dyken

    IPC: G06F17/50

    CPC classification number: G06F17/5031

    Abstract: A method for using computing equipment to perform timing analysis on an integrated circuit design includes identifying a timing arc of the integrated circuit design. The timing arc may be a clock path or a data path in the integrated circuit design. A probability of the timing arc may be obtained and an aging effect for the timing arc may be calculated. The aging effect of the timing arc is calculated based on the probability. The timing arc may include maximum and minimum delays that are adjusted based at least partly on the calculated aging effect on the timing arc.

    Abstract translation: 一种使用计算设备对集成电路设计进行定时分析的方法包括识别集成电路设计的定时弧。 定时电弧可以是集成电路设计中的时钟路径或数据路径。 可以获得定时弧的概率，并且可以计算定时弧的老化效应。 基于概率计算定时弧的老化效应。 定时弧可以包括至少部分地基于计时的对定时弧的老化效应来调整的最大和最小延迟。

    Method and Apparatus For Implementing Periphery Devices On A Programmable Circuit Using Partial Reconfiguration
    19.
    发明申请
    Method and Apparatus For Implementing Periphery Devices On A Programmable Circuit Using Partial Reconfiguration 有权
    在使用部分重配置的可编程电路上实现周边设备的方法和装置

    公开(公告)号：US20130263070A1

    公开(公告)日：2013-10-03

    申请号：US13902813

    申请日：2013-05-25

    Applicant: Altera Corporation

    Inventor： Kalen B. Brunham ,  Gordon Raymond Chiu ,  Joshua David Fender

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/505 ,  G06F17/5054 ,  G06F17/5077 ,  H03K19/17756 ,  H03K19/1776

    Abstract: A programmable circuit includes a physical interface at an input output (IO) periphery of the programmable circuit. The programmable circuit also includes a partial reconfigurable (PR) module, at the IO periphery of the programmable circuit, to implement a sequencer unit operable to configure the physical interface during a first instance of the PR module, and a controller unit operable to translate commands to the physical interface during a second instance of the PR module.

    Abstract translation: 可编程电路包括在可编程电路的输入输出（IO）外围的物理接口。 可编程电路还包括在可编程电路的IO周边的部分可重新配置（PR）模块，以实现可在PR模块的第一实例期间配置物理接口的定序器单元，以及可操作以将命令 在PR模块的第二个实例期间到物理接口。

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