Abstract:
A system may include a first microvia pad, a second microvia pad having a projection extending in a direction toward the first microvia pad, and a microvia electrically coupled to the first microvia pad and to the second microvia pad.
Abstract:
A ceramic package substrate has a recess. This allows a device in that recess to be close to a die attached to the substrate's top side, for better performance. The device may be an array capacitor, an in-silicon voltage regulator, or another device or devices.
Abstract:
A protective apparatus is disclosed. The apparatus includes a protective element for positioning over at least a portion of a device to protect the device in a first configuration. A support structure integral with the protective element also forms part of the apparatus. The support structure is configured to support the device in a second configuration. In one arrangement, the protective element includes a first surface and a second surface in which the first surface is configured to be at least partially positioned over and to face the device in the first configuration. The second surface is positioned opposite to the first surface and is configured to be exposed to the environment external to the device in the first configuration. In another arrangement, the support structure includes a slot that runs along the second surface in which the slot is configured to receive the device in the second configuration.
Abstract:
A system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period including a plurality of local edge generators receiving the clock signals, each local generator including local programmable means to record an absolute time at which to generate a timing signal in the current or future period and the means to generate that timing signal at a synchronous even sub-division of the clock period resolution. A separate time value is maintained allowing generated timing signals to be delayed by more than one period. An output delay circuit generates the timing signal responsive to a future time value and a phase offset. The phase offset can be provided using a clock multiplier and serial parallel converter to simplify hardware realizations.