公开(公告)号：US20230127749A1

公开(公告)日：2023-04-27

申请号：US18086308

申请日：2022-12-21

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Arun Chandrasekhar

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

公开(公告)号：US20220399324A1

公开(公告)日：2022-12-15

申请号：US17344348

申请日：2021-06-10

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Adel A. Elsherbini ,  Kimin Jun ,  Johanna M. Swan ,  Shawna M. Liff ,  Sathya Narasimman Tiagaraj ,  Gerald S. Pasdast ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00

Abstract: A die assembly comprising: a first component layer having conductive through-connections in an insulator, a second component layer comprising a die, and an active device layer (ADL) at an interface between the first component layer and the second component layer. The ADL comprises active elements electrically coupled to the first component layer and the second component layer. The die assembly further comprises a bonding layer electrically coupling the ADL to the second component layer. In some embodiments, the die assembly further comprises another ADL at another interface between the first component layer and a package support opposite to the interface. The first component layer may comprise another die having through-substrate vias (TSVs). The die and the another die may be fabricated using different process nodes.

公开(公告)号：US20220399294A1

公开(公告)日：2022-12-15

申请号：US17347394

申请日：2021-06-14

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Qiang Yu ,  Adel A. Elsherbini ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.

公开(公告)号：US20220399277A1

公开(公告)日：2022-12-15

申请号：US17345969

申请日：2021-06-11

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Scott E. Siers ,  Sathya Narasimman Tiagaraj ,  Gerald S. Pasdast ,  Zhiguo Qian ,  Kalyan C. Kolluru ,  Vivek Kumar Rajan ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: An Integrated Circuit (IC), comprising a first conductive trace on a first die, a second conductive trace on a second die, and a conductive pathway electrically coupling the first conductive trace with the second conductive trace. The second die is coupled to the first die with interconnects. The conductive pathway comprises a portion of the interconnects located proximate to a periphery of a region in the first die through which the first conductive trace is not routable. In some embodiments, the conductive pathway reroutes electrical connections away from the region. The region comprises a high congestion zone having high routing density in some embodiments. In other embodiments, the region comprises a “keep-out” zone.

公开(公告)号：US20220230964A1

公开(公告)日：2022-07-21

申请号：US17716229

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die comprising a first face and a second face; and a second die, the second die comprising a first face and a second face, wherein the second die further comprises a plurality of first conductive contacts at the first face and a plurality of second conductive contacts at the second face, and the second die is between first-level interconnect contacts of the microelectronic assembly and the first die.

公开(公告)号：US20220216182A1

公开(公告)日：2022-07-07

申请号：US17706156

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Amr Elshazly ,  Arun Chandrasekhar ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

公开(公告)号：US20220189861A1

公开(公告)日：2022-06-16

申请号：US17121093

申请日：2020-12-14

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.

公开(公告)号：US11348882B2

公开(公告)日：2022-05-31

申请号：US16683125

申请日：2019-11-13

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Johanna M. Swan ,  Adel A. Elsherbini ,  Veronica Aleman Strong

IPC: H01L23/60 ,  H01L23/498 ,  H01L23/053 ,  H01L23/00

Abstract: Embodiments may relate to a microelectronic package with an electrostatic discharge (ESD) protection structure within the package substrate. The ESD protection structure may include a cavity that has a contact of a signal line and a contact of a ground line positioned therein. Other embodiments may be described or claimed.

公开(公告)号：US11336559B2

公开(公告)日：2022-05-17

申请号：US16106926

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Tejpal Singh ,  Shawna M. Liff ,  Gerald S. Pasdast ,  Johanna M. Swan

IPC: H04L45/122 ,  H04L45/12 ,  H04L9/40 ,  G06F12/0842 ,  H04L49/109

Abstract: Embodiments herein may relate to a processor package with a substrate and a multi-chip processor coupled with the substrate. The multi-chip processor may include a dual-sided interconnect structure coupled with a first chip, a second chip, and a third chip. The first chip may be communicatively coupled with the second chip by an on-chip communication route. Likewise, the second chip may be communicatively coupled with the first chip by an on-chip communication route. Additionally, the first chip may be communicatively coupled with the third chip by a fast-lane communication route. Other embodiments may be described and/or claimed.

公开(公告)号：US11335663B2

公开(公告)日：2022-05-17

申请号：US16648354

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Arun Chandrasekhar

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.