公开(公告)号：US20200251448A1

公开(公告)日：2020-08-06

申请号：US16635501

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Beomseok Choi ,  Kaladhar Radhakrishnan ,  William Lambert ,  Michael Hill ,  Krishna Bharath

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00

Abstract: An apparatus is provided which comprises: a first set of one or more contacts on a first die surface, the first set of one or more contacts to couple with contacts of an integrated circuit die, one or more multi-level voltage clamps coupled with the first set of one or more contacts, the one or more multi-level voltage clamps switchable between two or more voltages, one or more integrated voltage regulators coupled with the one or more multi-level voltage clamps, the one or more integrated voltage regulators to provide an output voltage, one or more through silicon vias (TSVs) coupled with the one or more integrated voltage regulators, and a second set of one or more contacts on a second die surface, opposite the first die surface, the second set of one or more contacts coupled with the one or more TSVs, and the second set of one or more contacts to couple with contacts of a package substrate. Other embodiments are also disclosed and claimed.

公开(公告)号：US12100541B2

公开(公告)日：2024-09-24

申请号：US17020214

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  Adel A. Elsherbini

IPC: H01F27/28 ,  H01F27/10

CPC classification number: H01F27/2876 ,  H01F27/10

Abstract: An electronic package comprises, a package substrate, and a magnetic block, where the magnetic block passes through the package substrate. the electronic package further comprises a fluidic path from an inlet to the package substrate to an outlet of the package substrate. The electronic package further comprises a conductive winding in the package substrate, where the conductive winding wraps around the magnetic block, and where the conductive winding is tubular and the fluidic path passes through the conductive winding.

公开(公告)号：US20240063133A1

公开(公告)日：2024-02-22

申请号：US17891536

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Beomseok Choi ,  Feras Eid ,  Omkar Karhade ,  Shawna Liff

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L24/08 ,  H01L24/80 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/0652 ,  H01L23/3128 ,  H01L21/56 ,  H01L21/4853 ,  H01L2924/1434 ,  H01L2924/1432 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08225 ,  H01L2224/08145

Abstract: A multichip composite device includes on- and off-die metallization layers, inorganic dielectric material, and stacked hybrid-bonded dies. On-die metallization layers may be thinner than off-die metallization layers. The multichip composite device may include a structural substrate. Off-die metallization layers may be above and below the stacked hybrid-bonded dies. A substrate may couple the multichip composite device to a power supply in a multichip system. Forming a multichip composite device includes hybrid bonding dies and forming inorganic dielectric material.

公开(公告)号：US11710720B2

公开(公告)日：2023-07-25

申请号：US16022515

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  Siddharth Kulasekaran ,  Kaladhar Radhakrishnan

IPC: H01L25/065 ,  H01L25/18 ,  H02M1/08 ,  H02M3/158 ,  H02M1/00

CPC classification number: H01L25/0657 ,  H01L25/0652 ,  H01L25/18 ,  H02M1/08 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H02M1/0009 ,  H02M3/158

Abstract: A semiconductor package is provided, which includes a first die and a second die. The first die includes a first section of a power converter, and the second die includes a second section of the power converter. The power converter may include a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches. The PM circuitry may include a first part and a second part. The first section of the power converter in the first die may include the first part of the PM circuitry, and the second section of the power converter in the second die may include the second part of the PM circuitry.

公开(公告)号：US20230095654A1

公开(公告)日：2023-03-30

申请号：US17484213

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Stephen Morein ,  Krishna Bharath ,  Henning Braunisch ,  Beomseok Choi ,  Brandon M. Rawlings ,  Thomas L. Sounart ,  Johanna Swan ,  Yoshihiro Tomita ,  Aleksandar Aleksov

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48

Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US20220399305A1

公开(公告)日：2022-12-15

申请号：US17342826

申请日：2021-06-09

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  Adel A. Elsherbini ,  Han Wui Then ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/552 ,  H01L23/66 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, embedded in a first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a first magnetic conductive material; and a second microelectronic component, embedded in a second dielectric layer on the first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a second magnetic conductive material, wherein the second microelectronic component is coupled to the surface of the first microelectronic component by a hybrid bonding region, and wherein the second magnetic conductive material is coupled to the first magnetic conductive material.

公开(公告)号：US11527489B2

公开(公告)日：2022-12-13

申请号：US16024007

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Mathew Manusharow ,  Beomseok Choi ,  Digvijay Raorane

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/64 ,  G06F1/28 ,  H01F27/28 ,  H01F38/14 ,  H01L25/18

Abstract: An apparatus includes a substrate, one or more integrated circuit dies on the substrate, and a stiffener affixed to the substrate. One or more sections of the stiffener may includes a magnetic material. The apparatus further includes an inductive circuit element comprising one or more conductive structures wrapped around the magnetic material. In some examples where a first coil is wrapped around a first section of the stiffener, and a second coil is wrapped around a second section of the stiffener, current supplied to the first coil generates at the second coil a current that is further transmitted to the one or more semiconductor dies.

公开(公告)号：US20200004282A1

公开(公告)日：2020-01-02

申请号：US16020725

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： Beomseok Choi ,  Siddharth Kulasekaran ,  Krishna Bharath

IPC: G05F1/46 ,  H01L25/18 ,  H02M3/158 ,  H01L49/02

Abstract: An apparatus is provided, where the apparatus includes a first domain including first one or more circuitries, and a second domain including second one or more circuitries. The apparatus may further include a first voltage regulator (VR) to supply power to the first domain from a power bus, a second VR to supply power to the second domain from the power bus, and a third VR coupled between the first and second domains. The third VR may at least one of: transmit power to at least one of the first or second domains, or receive power from at least one of the first or second domains.

公开(公告)号：US12242290B2

公开(公告)日：2025-03-04

申请号：US17484286

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  William J. Lambert ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  Adel Elsherbini ,  Henning Braunisch ,  Stephen Morein ,  Aleksandar Aleksov ,  Feras Eid

IPC: G05F1/44 ,  H01L23/50 ,  H01L25/065

Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US12074514B2

公开(公告)日：2024-08-27

申请号：US17025745

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Kaladhar Radhakrishnan ,  Beomseok Choi ,  Michael Hill

IPC: H02M3/07 ,  H01L23/00 ,  H01L25/065 ,  H02M1/00

CPC classification number: H02M3/07 ,  H01L24/17 ,  H01L25/0655 ,  H01L2924/1427 ,  H02M1/0045 ,  H02M1/009

Abstract: Embodiments disclosed herein include two stage voltage regulators for electronic systems. In an embodiment, a voltage regulator comprises a switched capacitor voltage regulator (SCVR). In an embodiment, the SCVR receives a first voltage as an input and outputs a plurality of SCVR output voltages. In an embodiment, the voltage regulator further comprises a low-dropout (LDO) regulator. In an embodiment, the LDO regulator receives one or more of the plurality of SCVR output voltages as LDO input voltages, and where the LDO regulator outputs a second voltage.