公开(公告)号：US10522739B2

公开(公告)日：2019-12-31

申请号：US15735616

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Robert S. Chau

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02

Abstract: An embodiment includes an apparatus comprising: a substrate; and a perpendicular magnetic tunnel junction (pMTJ) comprising a fixed layer and first and second free layers; wherein (a) the first free layer includes Cobalt (Co), Iron (Fe), and Boron (B), and (b) the second free layer is epitaxial and includes Manganese (Mn) and Gallium (Ga). Other embodiments are described herein.

公开(公告)号：US10381556B2

公开(公告)日：2019-08-13

申请号：US15753478

申请日：2015-09-18

Applicant: INTEL CORPORATION

Inventor： Mark L. Doczy ,  Brian S. Doyle ,  Charles C. Kuo ,  Kaan Oguz ,  Kevin P. O'Brien ,  Satyarth Suri ,  Tejaswi K. Indukuri

IPC: H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  H01L43/10

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

公开(公告)号：US20250113573A1

公开(公告)日：2025-04-03

申请号：US18478691

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Andrey Vyatskikh ,  Paul B. Fischer ,  Uygar E. Avci ,  Chelsey Dorow ,  Mahmut Sami Kavrik ,  Karthik Krishnaswamy ,  Chia-Ching Lin ,  Jennifer Lux ,  Kirby Maxey ,  Carl Hugo Naylor ,  Kevin P. O'Brien ,  Justin R. Weber

IPC: H01L29/18 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78

Abstract: A low strain transfer protective layer is formed on a transition metal dichalcogenide (TMD) monolayer to enable the transfer of the TMD monolayer from a growth substrate to a target substrate with little or no strain-induced damage to the TMD monolayer. Transfer of a TMD monolayer from a growth substrate to a target substrate comprises two transfers, a first transfer from the growth substrate to a carrier wafer and a second transfer from the carrier wafer to the target substrate. Transfer of the TMD monolayer from the growth substrate to the carrier wafer comprises mechanically lifting off the TMD monolayer from the growth substrate. The low strain transfer protective layer can limit the amount of strain transferred from the carrier wafer to the TMD monolayer during lift-off. The carrier wafer and protective layer are separated from the TMD monolayer after attachment of the TMD monolayer to the target substrate.

公开(公告)号：US20250008852A1

公开(公告)日：2025-01-02

申请号：US18346212

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dominique A. Adams ,  Gauri Auluck ,  Scott B. Clendenning ,  Arnab Sen Gupta ,  Brandon Holybee ,  Raseong Kim ,  Matthew V. Metz ,  Kevin P. O'Brien ,  John J. Plombon ,  Marko Radosavljevic ,  Carly Rogan ,  Hojoon Ryu ,  Rachel A. Steinhardt ,  Tristan A. Tronic ,  I-Cheng Tung ,  Ian Alexander Young ,  Dmitri Evgenievich Nikonov

IPC: H10N70/00 ,  H10B63/00 ,  H10B99/00

Abstract: A two-terminal ferroelectric perovskite diode comprises a region of ferroelectric perovskite material positioned adjacent to a region of n-type doped perovskite semiconductor material. Asserting a positive voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a first direction that causes the diode to be placed in a low resistance state due to the formation of an accumulation region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor boundary. Asserting a negative voltage across the diode can cause the polarization of the ferroelectric perovskite material to be set in a second direction that causes the diode to be placed in a high resistance state due to the formation of a depletion region in the perovskite semiconductor material at the ferroelectric perovskite-perovskite semiconductor material. These non-volatile low and high resistance states enable the diode to be used as a non-volatile memory element.

公开(公告)号：US12062631B2

公开(公告)日：2024-08-13

申请号：US17025181

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A Elsherbini ,  Krishna Bharath ,  Kevin P. O'Brien ,  Kimin Jun ,  Han Wui Then ,  Mohammad Enamul Kabir ,  Gerald S. Pasdast ,  Feras Eid ,  Aleksandar Aleksov ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L23/00 ,  H01L25/065 ,  H01L49/02

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/05147 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/0801 ,  H01L2224/08145 ,  H01L2224/0903 ,  H01L2224/09055 ,  H01L2224/09505 ,  H01L2224/29186 ,  H01L2224/32145

Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

公开(公告)号：US20240120415A1

公开(公告)日：2024-04-11

申请号：US17958362

申请日：2022-10-01

Applicant: Intel Corporation

Inventor： Scott B. Clendenning ,  Sudarat Lee ,  Kevin P. O'Brien ,  Rachel A. Steinhardt ,  John J. Plombon ,  Arnab Sen Gupta ,  Charles C. Mokhtarzadeh ,  Gauri Auluck ,  Tristan A. Tronic ,  Brandon Holybee ,  Matthew V. Metz ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/778 ,  H01L21/02197 ,  H01L29/0665 ,  H01L29/66795 ,  H01L29/78391

Abstract: Technologies for a field effect transistor (FET) with a ferroelectric gate dielectric are disclosed. In an illustrative embodiment, a perovskite stack is grown on a buffer layer as part of manufacturing a transistor. The perovskite stack includes one or more doped semiconductor layers alternating with other lattice-matched layers. Growing the doped semiconductor layers on lattice-matched layers can improve the quality of the doped semiconductor layers. The lattice-matched layers can be etched away, leaving the doped semiconductor layers as fins for a ribbon FET. A ferroelectric layer can be conformally grown on the fins, creating a high-quality ferroelectric layer above and below the fins. A gate can then be grown on the ferroelectric layer.

公开(公告)号：US11935956B2

公开(公告)日：2024-03-19

申请号：US16913835

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl Naylor ,  Chelsey Dorow ,  Kirby Maxey ,  Tanay Gosavi ,  Ashish Verma Penumatcha ,  Shriram Shivaraman ,  Chia-Ching Lin ,  Sudarat Lee ,  Uygar E. Avci

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L21/02568 ,  H01L21/0262

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

公开(公告)号：US20230200081A1

公开(公告)日：2023-06-22

申请号：US17557119

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  John J. Plombon ,  Dmitri E. Nikonov ,  Kevin P. O'Brien ,  Ian A. Young ,  Matthew V. Metz ,  Chia-Ching Lin ,  Scott B. Clendenning ,  Punyashloka Debashish ,  Carly Lorraine Rogan ,  Brandon Jay Holybee ,  Kaan Oguz

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: Described herein are integrated circuit devices formed using perovskite materials. Perovskite materials with a similar crystal structure and different electrical properties can be layered to realize a transistor or memory device. In some embodiments, a ferroelectric perovskite can be incorporated into a device with other perovskite films to form a ferroelectric memory device.

公开(公告)号：US20220102495A1

公开(公告)日：2022-03-31

申请号：US17032669

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Kirby Kurtis Maxey ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Chelsey Jane Dorow ,  Kevin P. O'Brien ,  Shriram Shivaraman ,  Tanay Arun Gosavi ,  Uygar E. Avci

IPC: H01L29/08 ,  H01L29/24 ,  H01L29/78 ,  H01L29/66

Abstract: Disclosed herein are transistors including two-dimensional materials, as well as related methods and devices. In some embodiments, a transistor may include a first two-dimensional channel material and a second two-dimensional source/drain (S/D) material in a source/drain (S/D), and the first two-dimensional material and the second two-dimensional material may have different compositions or thicknesses. In some embodiments, a transistor may include a first two-dimensional material in a channel and a second two-dimensional material in a source/drain (S/D), wherein the first two-dimensional material is a single-crystal material, and the second two-dimensional material is a single-crystal material.

公开(公告)号：US20200043536A1

公开(公告)日：2020-02-06

申请号：US15735625

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Charles C. Kuo ,  Justin S. Brockman ,  Juan G. Alzate Vinasco ,  Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: An embodiment includes an apparatus comprising: a substrate; a perpendicular magnetic tunnel junction (pMTJ), on the substrate, comprising a first fixed layer, a second fixed layer, and a free layer between the first and second fixed layers; a first dielectric layer between the first fixed layer and the free layer; and a second layer between the second fixed layer and the free layer. Other embodiments are described herein.