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公开(公告)号：US20170285700A1
公开(公告)日：2017-10-05
申请号：US15086456
申请日：2016-03-31
Applicant: INTEL CORPORATION
Inventor： Daniel G. Cartagena , Corey D. Gough , Vivek Garg , Nikhil Gupta
CPC classification number: G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
Abstract: A dynamic adjustment of core power can reduce thermal margin between thermal design power (TDP) and an allowable thermal load. For example, by focusing directly on the core temperatures explicitly, a per-core closed loop temperature controller (pCLTC) can remove conservatism induced by the power level 1 policy (PL1, a policy which defines frequency and/or power for the processor under sustained load) thereby allowing for increased processor performance when there exists margin in the thermal system.
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公开(公告)号：US12066853B2
公开(公告)日：2024-08-20
申请号：US18329492
申请日：2023-06-05
Applicant: Intel Corporation
Inventor： Vasudevan Srinivasan , Krishnakanth V. Sistla , Corey D. Gough , Ian M. Steiner , Nikhil Gupta , Vivek Garg , Ankush Varma , Sujal A. Vora , David P. Lerner , Joseph M. Sullivan , Nagasubramanian Gurumoorthy , William J. Bowhill , Venkatesh Ramamurthy , Chris MacNamara , John J. Browne , Ripan Das
IPC: G06F1/08 , G06F1/3203 , G06F1/324 , G06F9/30 , G06F9/455
CPC classification number: G06F1/08 , G06F1/3203 , G06F1/324 , G06F9/30101 , G06F9/45558 , G06F2009/45591 , Y02D10/00
Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
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公开(公告)号：US20230315143A1
公开(公告)日：2023-10-05
申请号：US18329492
申请日：2023-06-05
Applicant: Intel Corporation
Inventor： Vasudevan Srinivasan , Krishnakanth V. Sistla , Corey D. Gough , Ian M. Steiner , Nikhil Gupta , Vivek Garg , Ankush Varma , Sujal A. Vora , David P. Lerner , Joseph M. Sullivan , Nagasubramanian Gurumoorthy , William J. Bowhill , Venkatesh Ramamurthy , Chris MacNamara , John J. Browne , Ripan Das
IPC: G06F1/08 , G06F1/3203 , G06F9/30 , G06F9/455 , G06F1/324
CPC classification number: G06F1/08 , G06F1/3203 , G06F9/30101 , G06F9/45558 , G06F1/324 , G06F2009/45591
Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.
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公开(公告)号：US11650851B2
公开(公告)日：2023-05-16
申请号：US16678888
申请日：2019-11-08
Applicant: Intel Corporation
Inventor： Stephen T. Palermo , Nikhil Gupta , Vasudevan Srinivasan , Christopher MacNamara , Sarita Maini , Abhishek Khade , Edwin Verplanke , Lokpraveen Mosur
CPC classification number: G06F9/505 , G06F9/45558 , G06F9/5044 , G06F2009/4557 , G06F2009/45595
Abstract: Methods, apparatus, systems and machine-readable storage media of an edge computing device using an edge server CPU with dynamic deterministic scaling is disclosed. A processing circuitry arrangement includes processing circuitry with processor cores operating at a center base frequency and memory. The memory includes instructions configuring the processing circuitry to configure a first set of the processor cores of the CPU to switch the operating at the center base frequency to operating at a first modified base frequency, and a second set of the processor cores to switch the operating at the center base frequency to operating at a second modified base frequency. A same processor core within the first set or the second set can be configured to switch operating between the first modified base frequency or the second modified base frequency.
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公开(公告)号：US11409560B2
公开(公告)日：2022-08-09
申请号：US16367581
申请日：2019-03-28
Applicant: Intel Corporation
Inventor： Krishnamurthy Jambur Sathyanarayana , Robert Valentine , Alexander Gendler , Shmuel Zobel , Gavri Berger , Ian M. Steiner , Nikhil Gupta , Eyal Hadas , Edo Hachamo , Sumesh Subramanian
IPC: G06F9/48 , G06F9/38 , G06F9/30 , G06F9/4401 , G06F1/3206 , G06F1/324 , G06F1/3234 , G06F1/3296
Abstract: In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.
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Patent Agency Ranking
16.发明授权公开(公告)号：US11194373B2
公开(公告)日：2021-12-07
申请号：US16853570
申请日：2020-04-20
Applicant: Intel Corporation
Inventor： Asma Al-Rawi , Federico Ardanaz , Jonathan M. Eastep , Nikhil Gupta , Ankush Varma , Krishnakanth V. Sistla , Ian M. Steiner
IPC: G06F1/26 , G06F1/32 , G06F1/3206 , G06F1/324 , H04L12/12 , G06F1/3228 , G06F1/20
Abstract: Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned ‘weights’ based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.
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公开(公告)号：US11144085B2
公开(公告)日：2021-10-12
申请号：US15632000
申请日：2017-06-23
Applicant: Intel Corporation
Inventor： Asma H. Al-Rawi , Federico Ardanaz , Jonathan M. Eastep , Dorit Shapira , Krishnakanth Sistla , Nikhil Gupta , Vasudevan Srinivasan , Chris MacNamara
Abstract: An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.
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公开(公告)号：US10474208B2
公开(公告)日：2019-11-12
申请号：US15086456
申请日：2016-03-31
Applicant: INTEL CORPORATION
Inventor： Daniel G. Cartagena , Corey D. Gough , Vivek Garg , Nikhil Gupta
IPC: G06F1/20 , G06F1/32 , G06F1/3206 , G06F1/324 , G06F1/3296
Abstract: A dynamic adjustment of core power can reduce thermal margin between thermal design power (TDP) and an allowable thermal load. For example, by focusing directly on the core temperatures explicitly, a per-core closed loop temperature controller (pCLTC) can remove conservatism induced by the power level 1 policy (PL1, a policy which defines frequency and/or power for the processor under sustained load) thereby allowing for increased processor performance when there exists margin in the thermal system.
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19.发明申请公开(公告)号：US20190041925A1
公开(公告)日：2019-02-07
申请号：US15938291
申请日：2018-03-28
Applicant: Intel Corporation
Inventor： Sandeep Ahuja , Nikhil Gupta , Vasudevan Srinivasan
Abstract: In one embodiment, a processor includes a non-volatile storage to store a plurality of configurations for the processor, the non-volatile storage including a plurality of entries to store configuration information for the processor for one of the plurality of configurations, the configuration information including at least one of a guaranteed operating frequency and a core count, at least one of the entries to store the core count. The processor further includes a power controller to control the processor to operate at one of the plurality of configurations based at least in part on a selected thermal set point of a plurality of thermal set points of the processor, each of the plurality of thermal set points associated with one of the configurations. Other embodiments are described and claimed.
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公开(公告)号：US11886918B2
公开(公告)日：2024-01-30
申请号：US17717859
申请日：2022-04-11
Applicant: INTEL CORPORATION
Inventor： Ankush Varma , Nikhil Gupta , Vasudevan Srinivasan , Krishnakanth Sistla , Nilanjan Palit , Abhinav Karhu , Eugene Gorbatov , Eliezer Weissmann
CPC classification number: G06F9/5027 , G06F9/4812 , G06F9/4881 , G06F9/542 , G06F15/8038
Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.
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